mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-09 13:15:21 +00:00
984bfae831
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and .yaml files. Will avoid failures with the new CI test in https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only checks changed files. Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst to get rid of the trailing blank line there. It was probably misplaced. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
34 lines
897 B
C
34 lines
897 B
C
/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "spi_context.h"
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#define SPI_OC_SIMPLE_DATA(dev) \
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((struct spi_oc_simple_data *) ((dev)->driver_data))
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#define SPI_OC_SIMPLE_REG(info, offset) \
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((mem_addr_t) (info->base + \
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(offset * CONFIG_SPI_OC_SIMPLE_BUS_WIDTH / 8)))
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#define SPI_OC_SIMPLE_SPCR(dev) SPI_OC_SIMPLE_REG(dev, 0x0)
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#define SPI_OC_SIMPLE_SPSR(dev) SPI_OC_SIMPLE_REG(dev, 0x1)
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#define SPI_OC_SIMPLE_SPDR(dev) SPI_OC_SIMPLE_REG(dev, 0x2)
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#define SPI_OC_SIMPLE_SPER(dev) SPI_OC_SIMPLE_REG(dev, 0x3)
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#define SPI_OC_SIMPLE_SPSS(dev) SPI_OC_SIMPLE_REG(dev, 0x4)
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#define SPI_OC_SIMPLE_SPCR_SPE BIT(6)
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#define SPI_OC_SIMPLE_SPCR_CPOL BIT(3)
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#define SPI_OC_SIMPLE_SPCR_CPHA BIT(2)
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struct spi_oc_simple_cfg {
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u32_t base;
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u32_t f_sys;
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};
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struct spi_oc_simple_data {
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struct spi_context ctx;
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};
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