mirror of
https://github.com/zephyrproject-rtos/zephyr
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21fbc9b07e
Supports STM32 F1/F4 (v1 controller) and STM32 F3/L4X (v2 controller) v1 could also support L1X. v2 could also support F7X. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com> Reviewed-by: Yannis Damigos <giannis.damigos@gmail.com> Tested-by: Yannis Damigos <giannis.damigos@gmail.com> Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
/*
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* Copyright (c) 2016 BayLibre, SAS
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* Copyright (c) 2017 Linaro Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#ifndef _STM32_I2C_H_
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#define _STM32_I2C_H_
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typedef void (*irq_config_func_t)(struct device *port);
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struct i2c_stm32_config {
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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irq_config_func_t irq_config_func;
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#endif
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struct stm32_pclken pclken;
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I2C_TypeDef *i2c;
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};
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struct i2c_stm32_data {
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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struct k_sem device_sync_sem;
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#endif
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union dev_config dev_config;
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#ifdef CONFIG_I2C_STM32_V1
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u16_t slave_address;
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#endif
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struct {
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#ifdef CONFIG_I2C_STM32_V1
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unsigned int is_restart;
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unsigned int flags;
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#endif
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unsigned int is_write;
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unsigned int is_nack;
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unsigned int is_err;
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struct i2c_msg *msg;
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unsigned int len;
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u8_t *buf;
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} current;
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};
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s32_t stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg, u32_t flg,
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u16_t sadr);
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s32_t stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg, u32_t flg,
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u16_t sadr);
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s32_t stm32_i2c_configure_timing(struct device *dev, u32_t clk);
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void stm32_i2c_event_isr(void *arg);
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void stm32_i2c_error_isr(void *arg);
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#define DEV_DATA(dev) ((struct i2c_stm32_data * const)(dev)->driver_data)
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#define DEV_CFG(dev) \
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((const struct i2c_stm32_config * const)(dev)->config->config_info)
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#endif /* _STM32_I2C_H_ */
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