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https://github.com/zephyrproject-rtos/zephyr
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79edb8b632
stm32wb55rg is a dual core SoC (M4/M0) with a radio/protocol stack running on M0 core. M0 FW starts at flash address 0x80CB000. So flash size available to zephyr is 812K instead of 1M. Configure package size to reflect this (flash size is now 812K) and update MPU setting to exclude M0 FW. From MPU point of view, we set flash size to 512K since we should chose a size being a power of 2. If we consider there will be 2 images partitions in a FOTA scheme, 512 K is beyond image-0 and hence is sufficient to cover application image. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
94 lines
2.9 KiB
C
94 lines
2.9 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARM_MPU_MEM_CFG_H_
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#define _ARM_MPU_MEM_CFG_H_
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#include <soc.h>
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#include <arch/arm/cortex_m/mpu/arm_mpu.h>
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/* Flash Region Definitions */
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#if !defined(CONFIG_SOC_SERIES_STM32WBX)
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#if CONFIG_FLASH_SIZE == 64
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#define REGION_FLASH_SIZE REGION_64K
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#elif CONFIG_FLASH_SIZE == 128
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#define REGION_FLASH_SIZE REGION_128K
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#elif CONFIG_FLASH_SIZE == 256
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#define REGION_FLASH_SIZE REGION_256K
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#elif CONFIG_FLASH_SIZE == 512
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#define REGION_FLASH_SIZE REGION_512K
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#elif CONFIG_FLASH_SIZE == 1024
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#define REGION_FLASH_SIZE REGION_1M
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#elif CONFIG_FLASH_SIZE == 1536
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#define REGION_FLASH_SIZE REGION_2M /* last 512kB are not mapped */
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#elif CONFIG_FLASH_SIZE == 2048
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#define REGION_FLASH_SIZE REGION_2M
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#else
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#error "Unsupported configuration"
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#endif
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#else /* CONFIG_SOC_SERIES_STM32WBX */
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/* For STM32WBX SoCs, last 212K are resevred for M0 fw */
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/* and should not be covered by zephyr MPU. */
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/* So map only the first 512K, which is beyond partition 'image-0' */
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#if CONFIG_FLASH_SIZE == 812
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#define REGION_FLASH_SIZE REGION_1M
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#else
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#error "Unsupported configuration"
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#endif
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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/* SRAM Region Definitions */
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#if CONFIG_SRAM_SIZE == 12
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#define REGION_SRAM_0_SIZE REGION_8K
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#define REGION_SRAM_1_START 0x2000
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#define REGION_SRAM_1_SIZE REGION_4K
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#elif CONFIG_SRAM_SIZE == 20
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#define REGION_SRAM_0_SIZE REGION_16K
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#define REGION_SRAM_1_START 0x4000
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#define REGION_SRAM_1_SIZE REGION_4K
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#elif CONFIG_SRAM_SIZE == 32
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#define REGION_SRAM_0_SIZE REGION_32K
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#elif CONFIG_SRAM_SIZE == 40
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#define REGION_SRAM_0_SIZE REGION_32K
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#define REGION_SRAM_1_START 0x8000
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#define REGION_SRAM_1_SIZE REGION_8K
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#elif CONFIG_SRAM_SIZE == 64
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#define REGION_SRAM_0_SIZE REGION_64K
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#elif CONFIG_SRAM_SIZE == 96
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#define REGION_SRAM_0_SIZE REGION_64K
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#define REGION_SRAM_1_START 0x10000
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#define REGION_SRAM_1_SIZE REGION_32K
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#elif CONFIG_SRAM_SIZE == 128
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#define REGION_SRAM_0_SIZE REGION_128K
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#elif CONFIG_SRAM_SIZE == 160
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#define REGION_SRAM_0_SIZE REGION_128K
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#define REGION_SRAM_1_START 0x20000
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#define REGION_SRAM_1_SIZE REGION_32K
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#elif CONFIG_SRAM_SIZE == 192
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#define REGION_SRAM_0_SIZE REGION_128K
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#define REGION_SRAM_1_START 0x20000
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#define REGION_SRAM_1_SIZE REGION_64K
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#elif CONFIG_SRAM_SIZE == 256
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#define REGION_SRAM_0_SIZE REGION_256K
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#elif CONFIG_SRAM_SIZE == 320
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#define REGION_SRAM_0_SIZE REGION_256K
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#define REGION_SRAM_1_START 0x40000
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#define REGION_SRAM_1_SIZE REGION_64K
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#elif CONFIG_SRAM_SIZE == 384
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#define REGION_SRAM_0_SIZE REGION_256K
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#define REGION_SRAM_1_START 0x40000
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#define REGION_SRAM_1_SIZE REGION_128K
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#elif CONFIG_SRAM_SIZE == 512
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#define REGION_SRAM_0_SIZE REGION_512K
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#elif CONFIG_SRAM_SIZE == 640
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#define REGION_SRAM_0_SIZE REGION_512K
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#define REGION_SRAM_1_START 0x80000
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#define REGION_SRAM_1_SIZE REGION_128K
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#else
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#error "Unsupported configuration"
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#endif
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#endif /* _ARM_MPU_MEM_CFG_H_ */
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