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https://github.com/zephyrproject-rtos/zephyr
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ac74d8b652
Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
140 lines
3.6 KiB
Plaintext
140 lines
3.6 KiB
Plaintext
# Kconfig - STM32F4 MCU clock control driver config
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#
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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# Copyright (c) Linaro Limited.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_STM32F4X
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menuconfig CLOCK_CONTROL_STM32F4X
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bool
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prompt "STM32F4X Reset & Clock Control"
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default y if SOC_SERIES_STM32F4X
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help
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Enable driver for Reset & Clock Control subsystem found
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in STM32F4 family of MCUs
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config CLOCK_CONTROL_STM32F4X_DEVICE_INIT_PRIORITY
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int "Clock Control Device Priority"
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default 1
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depends on CLOCK_CONTROL_STM32F4X
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help
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This option controls the priority of clock control
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device initialization. Higher priority ensures that the device
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is initialized earlier in the startup cycle. If unsure, leave
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at default value 1
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choice
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prompt "STM32F4X System Clock Source"
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depends on CLOCK_CONTROL_STM32F4X
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config CLOCK_STM32F4X_SYSCLK_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of SYSCLK
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config CLOCK_STM32F4X_SYSCLK_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of SYSCLK
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config CLOCK_STM32F4X_SYSCLK_SRC_PLL
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bool "PLL"
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help
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Use PLL as source of SYSCLK
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endchoice
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choice
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prompt "STM32F4X PLL Clock Source"
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depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL
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config CLOCK_STM32F4X_PLL_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of PLL
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config CLOCK_STM32F4X_PLL_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of PLL
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endchoice
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config CLOCK_STM32F4X_HSE_BYPASS
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bool "HSE bypass"
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depends on CLOCK_CONTROL_STM32F4X && (CLOCK_STM32F4X_PLL_SRC_HSE || CLOCK_STM32F4X_SYSCLK_SRC_HSE)
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help
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Enable this option to bypass external high-speed clock (HSE).
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config CLOCK_STM32F4X_PLLM_DIV_FACTOR
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int "Division factor for PLL VCO input clock"
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depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL
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default 8
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range 2 63
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help
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PLLM division factor needs to be set correctly to ensure that the VCO
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input frequency ranges from 1 to 2 MHz. It is recommended to select a
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frequency of 2 MHz to limit PLL jitter.
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Allowed values: 2-63
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config CLOCK_STM32F4X_PLLN_MULTIPLIER
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int "Multiplier factor for PLL VCO output clock"
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depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL
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default 336
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range 192 432
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help
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PLLN multiplier factor needs to be set correctly to ensure that the
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VCO output frequency is between 192 and 432 MHz.
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Allowed values: 192-432
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config CLOCK_STM32F4X_PLLP_DIV_FACTOR
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int "PLL division factor for main system clock"
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depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL
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default 4
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range 2 8
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help
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PLLP division factor needs to be set correctly to not exceed 84MHz.
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Allowed values: 2, 4, 6, 8
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config CLOCK_STM32F4X_PLLQ_DIV_FACTOR
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int "Division factor for OTG FS, SDIO and RNG clocks"
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depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL
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default 7
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range 2 15
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help
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The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
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need a frequency lower than or equal to 48 MHz to work correctly.
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Allowed values: 2-15
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config CLOCK_STM32F4X_AHB_PRESCALER
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int "AHB prescaler"
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depends on CLOCK_CONTROL_STM32F4X
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default 0
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range 0 512
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help
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AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32F4X_APB1_PRESCALER
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int "APB1 low speed clock prescaler"
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depends on CLOCK_CONTROL_STM32F4X
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default 2
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range 0 16
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help
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APB1 Low speed clock (PCLK1) prescaler, allowed values:
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0, 2, 4, 8, 16. The APB1 clock must not exceed 42MHz.
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config CLOCK_STM32F4X_APB2_PRESCALER
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int "APB2 high speed clock prescaler"
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depends on CLOCK_CONTROL_STM32F4X
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default 0
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range 0 16
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help
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APB2 High speed clock (PCLK2) prescaler, allowed values:
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0, 2, 4, 8, 16. The APB2 clock must not exceed 84MHz.
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endif
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