zephyrproject-rtos/zephyr
0
0
Fork 0
mirror of https://github.com/zephyrproject-rtos/zephyr synced 2025-09-02 12:23:03 +00:00
Code Issues Packages Projects Releases Wiki Activity
2ea71a9f80
zephyr/soc/riscv
History
Daniel Leung 8a79ce1428 riscv: add support for thread local storage 
Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-10-24 10:52:00 -07:00
..
litex-vexriscv
openisa_rv32m1 riscv: add support for thread local storage 2020-10-24 10:52:00 -07:00
riscv-privilege
CMakeLists.txt