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https://github.com/zephyrproject-rtos/zephyr
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2805ea9193
Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
99 lines
2.0 KiB
Plaintext
99 lines
2.0 KiB
Plaintext
# Kconfig - STM32H7 PLL configuration options
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#
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# Copyright (c) 2019 Linaro
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_STM32H7X
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# Bus clocks configuration options
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config CLOCK_STM32_D1CPRE
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int "D1 Domain, CPU1 clock prescaler"
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default 1
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range 1 512
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help
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D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler),
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allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.
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config CLOCK_STM32_HPRE
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int "hclk prescaler, D2 domain (CPU2) Clock prescaler"
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default 1
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range 1 512
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help
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hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.
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config CLOCK_STM32_D2PPRE1
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int "APB1 prescaler"
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default 1
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range 1 16
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help
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APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16
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config CLOCK_STM32_D2PPRE2
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int "D2 DOMAIN, APB2 prescaler"
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default 1
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range 1 16
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help
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APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16
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config CLOCK_STM32_D1PPRE
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int "D1 DOMAIN, APB3 prescaler"
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default 1
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range 1 16
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help
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APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16
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config CLOCK_STM32_D3PPRE
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int "APB4 prescaler"
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default 1
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range 1 16
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help
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APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16
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# PLL settings
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config CLOCK_STM32_PLL_M_DIVISOR
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int "PLL divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 32
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range 0 63
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help
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PLL divisor, allowed values: 0-63.
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "PLL1 VCO multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 129
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range 4 512
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help
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PLL multiplier, allowed values: 4-512.
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL P Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 1 128
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help
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PLL P Output divisor, allowed values: 1-128.
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "PLL Q Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 1 128
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help
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PLL Q Output divisor, allowed values: 1-128.
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config CLOCK_STM32_PLL_R_DIVISOR
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int "PLL R Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 1 128
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help
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PLL R Output divisor, allowed values: 1-128.
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endif # SOC_SERIES_STM32H7X
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