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MEC1501 RTOS timer internal counter is on the 32KHz clock domain. The register interface is on the AHB clock. When the timer is started hardware synchronizes to the next 32KHz clock edge resulting is a variable delay moving the value in the preload register into the count register. The maximum delay is one 32KHz clock period (30.5 us). We work-around this delay by checking if the timer has been started and not using the count value which is still 0. Instead we state zero counts have elapsed. Signed-off-by: Scott Worley <scott.worley@microchip.com> |
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.. | ||
altera_avalon_timer_hal.c | ||
apic_timer.c | ||
arcv2_timer0.c | ||
CMakeLists.txt | ||
cortex_m_systick.c | ||
hpet.c | ||
Kconfig | ||
legacy_api.h | ||
litex_timer.c | ||
loapic_timer.c | ||
mchp_xec_rtos_timer.c | ||
native_posix_timer.c | ||
nrf_rtc_timer.c | ||
riscv_machine_timer.c | ||
rv32m1_lptmr_timer.c | ||
sam0_rtc_timer.c | ||
sys_clock_init.c | ||
xlnx_psttc_timer.c | ||
xtensa_sys_timer.c |