mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-14 07:21:56 +00:00
33eabf6fc7
Adds native_posix hw counter model and the counter driver. Functionality is needed by software which is tested on native_posix and has dependency on counter. Hardware model was developed similarly to HW timer model. The counter driver wraps HW counter functions and exposes basic functionalities: starting, stopping, setting and cancelling single channel alarms. Code was tested against: tests/drivers/counter/counter_basic_api. Signed-off-by: Filip Zajdel <filip.zajdel@nordicsemi.no>
49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
/*
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* Copyright (c) 2017 Oticon A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file Extra definitions provided by the board to soc.h
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*
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* Background:
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* The POSIC ARCH/SOC/board layering is different than in normal archs
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* The "SOC" does not provide almost any of the typical SOC functionality
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* but that is left for the "board" to define it
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* Device code may rely on the soc.h defining some things (like the interrupts
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* numbers)
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* Therefore this file is included from the inf_clock soc.h to allow a board
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* to define that kind of SOC related snippets
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*/
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#ifndef _POSIX_SP_BOARD_SOC_H
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#define _POSIX_SP_BOARD_SOC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define TIMER_TICK_IRQ 0
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#define OFFLOAD_SW_IRQ 1
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#define COUNTER_EVENT_IRQ 2
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/*
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* This interrupt will awake the CPU if IRQs are not locked,
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* This interrupt does not have an associated status bit or handler
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*/
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#define PHONY_WEAK_IRQ 0xFFFE
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/*
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* This interrupt will awake the CPU even if IRQs are locked,
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* This interrupt does not have an associated status bit or handler
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* (the lock is only ignored when the interrupt is raised from the HW models,
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* SW threads should not try to use this)
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*/
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#define PHONY_HARD_IRQ 0xFFFF
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#ifdef __cplusplus
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}
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#endif
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#endif /* _POSIX_SP_BOARD_SOC_H */
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