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https://github.com/zephyrproject-rtos/zephyr
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857ed0a380
The nrf52 bsim hw models now require some of these to be defined. For this case we cannot implement these as static inline functions as that would redefinitions of the functions. Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
46 lines
726 B
C
46 lines
726 B
C
/*
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* Copyright (c) 2020 Oticon A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* This header defines replacements for inline
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* ARM Cortex-M CMSIS intrinsics.
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*/
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#ifndef BOARDS_POSIX_NRF52_BSIM_CMSIS_H
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#define BOARDS_POSIX_NRF52_BSIM_CMSIS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Implement the following ARM intrinsics as no-op:
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* - ARM Data Synchronization Barrier
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* - ARM Data Memory Synchronization Barrier
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* - ARM Instruction Synchronization Barrier
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* - ARM No Operation
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*/
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#ifndef __DMB
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#define __DMB()
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#endif
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#ifndef __DSB
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#define __DSB()
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#endif
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#ifndef __ISB
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#define __ISB()
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#endif
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#ifndef __NOP
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#define __NOP()
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARDS_POSIX_NRF52_BSIM_CMSIS_H */
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