Rajavardhan Gundi dadf9e7a81 xtensa: intel_s1000: implement interrupt mechanism ... intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>		2018-05-01 16:46:41 -04:00
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arcv2_irq_unit.c
cavs_ictl.c	drivers: interrupts: introduce CAVS interrupt logic	2018-05-01 16:46:41 -04:00
cavs_ictl.h	drivers: interrupts: introduce CAVS interrupt logic	2018-05-01 16:46:41 -04:00
CMakeLists.txt	drivers: interrupts: introduce Designware interrupt controller	2018-05-01 16:46:41 -04:00
dw_ictl.c	drivers: interrupts: introduce Designware interrupt controller	2018-05-01 16:46:41 -04:00
dw_ictl.h	drivers: interrupts: introduce Designware interrupt controller	2018-05-01 16:46:41 -04:00
exti_stm32.c
exti_stm32.h
i8259.c
ioapic_intr.c
ioapic_priv.h
Kconfig	xtensa: intel_s1000: implement interrupt mechanism	2018-05-01 16:46:41 -04:00
Kconfig.multilevel
Kconfig.s1000	drivers: interrupts: introduce CAVS interrupt logic	2018-05-01 16:46:41 -04:00
Kconfig.shared_irq
Kconfig.stm32
loapic_intr.c
loapic_spurious.S
mvic.c
plic_fe310.c
shared_irq.c
system_apic.c