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https://github.com/zephyrproject-rtos/zephyr
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814403a4f5
The VMURT1170 board configures the FLEXSPI to run at 200MHz serial clock in DDR mode, via the flash configuration block passed to the ROM API. Per the datasheet of the MX25UM51345G flash present on the board, 20 dummy cycles are required before reading data in OPI DTR mode. Correct the dummy cycle value used for read commands to 0x28 (40 DDR dummy cycles, equivalent to 20 dummy cycles of the clock) to resolve this issue. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
151 lines
4.3 KiB
C
151 lines
4.3 KiB
C
/*
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* Copyright (c) 2019, MADMACHINE LIMITED
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* Copyright 2024 NXP
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*
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* refer to hal_nxp board file
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <flexspi_nor_config.h>
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/*!
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* @brief ROM API init
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*
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* Get the bootloader api entry address.
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*/
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void ROM_API_Init(void);
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/*!
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* @brief Initialize Serial NOR devices via FLEXSPI
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*
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* This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.
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*
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* @param instance storage the instance of FLEXSPI.
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* @param config A pointer to the storage for the driver runtime state.
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*
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* @retval kStatus_Success Api was executed successfully.
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* @retval kStatus_InvalidArgument A invalid argument is provided.
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* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
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* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
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* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
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*/
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status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, struct flexspi_nor_config_t *config);
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#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.conf"
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#endif
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/* Config used for booting */
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const struct flexspi_nor_config_t Qspiflash_config = {
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.memConfig = {
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc =
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kFlexSPIReadSampleClk_LoopbackInternally,
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.csHoldTime = 1u,
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.csSetupTime = 1u,
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.sflashPadType = kSerialFlash_1Pad,
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.serialClkFreq = kFlexSpiSerialClk_80MHz,
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.sflashA1Size = 64u * 1024u * 1024u,
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.lookupTable = {
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
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0x03, RADDR_SDR,
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FLEXSPI_1PAD, 0x18),
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FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD,
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0x04, STOP,
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FLEXSPI_1PAD, 0),
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.blockSize = 64u * 1024u,
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.isUniformBlockSize = false,
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};
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#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */
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/* Config used for code execution */
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const struct flexspi_nor_config_t g_flash_fast_config = {
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.memConfig = {
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
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.csHoldTime = 1,
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.csSetupTime = 1,
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.deviceModeCfgEnable = 1,
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.deviceModeType = kDeviceConfigCmdType_Spi2Xpi,
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.waitTimeCfgCommands = 1,
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.deviceModeSeq = {
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.seqNum = 1,
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.seqId = 6, /* See Lookup table for more details */
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.reserved = 0,
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},
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.deviceModeArg = 2, /* Enable OPI DDR mode */
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.controllerMiscOption =
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(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable)
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| (1u << kFlexSpiMiscOffset_DdrModeEnable),
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_8Pads,
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.serialClkFreq = kFlexSpiSerialClk_200MHz,
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.sflashA1Size = 64ul * 1024u * 1024u,
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.busyOffset = 0u,
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.busyBitPolarity = 0u,
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.lookupTable = {
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/* Read */
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[0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD,
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0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11),
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[0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD,
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0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x28),
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[0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD,
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0x04, STOP, FLEXSPI_1PAD, 0x00),
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/* Write enable SPI */
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[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
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0x06, STOP, FLEXSPI_1PAD, 0x00),
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/*Write Configuration Register 2 =01, Enable OPI DDR mode*/
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[4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
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0x72, CMD_SDR, FLEXSPI_1PAD, 0x00),
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[4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
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0x00, CMD_SDR, FLEXSPI_1PAD, 0x00),
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[4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
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0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01),
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.blockSize = 64u * 1024u,
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.isUniformBlockSize = false,
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.ipcmdSerialClkFreq = 1,
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.serialNorType = 2,
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.reserve2[0] = 0x7008200,
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};
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__ramfunc int imxrt_reclock_initialize(void)
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{
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const uint32_t instance = 1;
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volatile struct flexspi_nor_config_t bootConfig;
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memcpy((struct flexspi_nor_config_t *)&bootConfig, &g_flash_fast_config,
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sizeof(struct flexspi_nor_config_t));
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bootConfig.memConfig.tag = FLEXSPI_CFG_BLK_TAG;
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ROM_API_Init();
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ROM_FLEXSPI_NorFlash_Init(instance, (struct flexspi_nor_config_t *)&bootConfig);
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return 0;
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}
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SYS_INIT(imxrt_reclock_initialize, PRE_KERNEL_1, 0);
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