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The Intel S1000 board has a SPI flash that isn't directly MMIO addressable. For this case we shouldn't generate CONFIG_FLASH_SIZE or CONFIG_FLASH_BASE_ADDRESS. We use the heuristic of assuming if the flash node #size-cells is 0, its a SPI flash. Than if the parent node (SPI controller) has only a single reg element we assume its a non-MMIO addressable SPI flash. If there is more than one reg element we assume the last reg element is the MMIO address region for access to the flash. Fixes #12530 Signed-off-by: Kumar Gala <kumar.gala@linaro.org> |
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extract | ||
devicetree.py | ||
extract_dts_includes.py |