mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-13 08:41:57 +00:00
1f4b5ddd0f
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
49 lines
735 B
Plaintext
49 lines
735 B
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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/dts-v1/;
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#include <riscv32-fe310.dtsi>
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/ {
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model = "SiFive HiFive 1";
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compatible = "sifive,hifive1";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &dtim;
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zephyr,flash = &flash0;
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};
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};
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&gpio0 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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clock-frequency = <16000000>;
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};
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&uart1 {
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clock-frequency = <16000000>;
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};
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&spi0 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10014000 0x1000 0x20400000 0xc00000>;
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flash0: flash@0 {
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compatible = "issi,is25lp128", "jedec,spi-nor";
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label = "FLASH0";
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jedec-id = [96 60 18];
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reg = <0>;
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// Dummy entry
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spi-max-frequency = <0>;
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};
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};
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