Filip Kokosinski 342cbc9e01 soc: riscv32: add LiteX VexRiscV SoC ... Add LiteX with softcore CPU VexRiscV SoC definitions and default configurations. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>		2019-05-15 12:52:16 -05:00
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arc	boards: iotdk: add mpu and fpu configuration	2019-04-29 09:03:24 -07:00
arm	dts: nordic: add missing erase-block-size entry	2019-05-15 11:05:19 -05:00
bindings	drivers: interrupt_controller: add LiteX interrupt controller driver	2019-05-15 12:52:16 -05:00
common	dts: flash simulator cleanup	2019-04-26 04:04:19 -07:00
nios2	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00
riscv32	soc: riscv32: add LiteX VexRiscV SoC	2019-05-15 12:52:16 -05:00
x86	boards/x86/up_squared: move UART configuration to apollo_lake.dtsi	2019-05-04 18:29:32 -04:00
xtensa	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00
Kconfig	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00