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https://github.com/zephyrproject-rtos/zephyr
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995a9ba72a
Support for Freescale/NXP K64 SPI modules, limited to: - Master mode - A single active set of clock and transfer attributes (CTAR0), which includes non-adjustable delay parameters - Tx FIFO fill and Rx FIFO drain interrupt handling - Standard, continuous select and continuous SCK SPI transfer formats Also, divide-by-zero code generation in this driver is prevented. The 'volatile' attribute is added to some of the variables in the baud rate and delay calculation functions of the K64 SPI driver in order to prevent bad code generation by gcc toolchains for ARM seen when an optimization setting above -O0 is used. Specifically, a register is loaded with the constant 0 and is used as the divisor in a following divide instruction, resulting in a divide-by-zero exception. This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain) and 5.2.0 (the Zephyr SDK toolchain). Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
79 lines
2.9 KiB
C
79 lines
2.9 KiB
C
/* spi_k64.h - Freescale K64 SPI controller driver utilities */
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/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __SPI_K64_H__
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#define __SPI_K64_H__
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/*
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* Device configuration
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*
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* Device-independent configuration:
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* Bits [0 : 11] in the config parameter of the spi_configure() API are defined
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* with the following fields.
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*
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* SCK polarity [ 0 ] - SCK inactive state (0 = low, 1 = high)
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* SCK phase [ 1 ] - Data captured/changed on which SCK edge:
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* - 0 = leading/following edges, respectively
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* - 1 = following/leading edges, respectively
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* loop_mode [ 2 ] - Not used/Unsupported
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* transfer_mode [ 3 ] - First significant bit (0 = MSB, 1 = LSB)
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* word_size [ 4 : 7 ] - Size of a data train in bits
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* unused [ 8 : 11 ] - Unused word_size field bits
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*
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* Device-specific configuration:
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* Bits [12 : 31] in the config parameter of the spi_configure() API are
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* available, with the following fields defined for this device.
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*
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* PCS0-5 polarity [ 12 : 17 ] - Periph. Chip Select inactive state, MCR[PCSIS]
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* - (0 = low, 1 = high)
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* Continuous SCK [ 18 ] - Continuous serial clocking, MCR[CONT_SCKE]
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* - (0 = disabled, 1 = enabled)
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* Continuous PCS [ 19 ] - Continuous selection format, PUSHR[CONT]
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* - (0 = disabled, 1 = enabled)
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*
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* Note that the number of valid PCS signals differs for each
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* K64 SPI module:
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* - SPI0 uses PCS0-5;
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* - SPI1 uses PCS0-3;
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* - SPI2 uses PCS0-1;
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*/
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/* PCS polarity access macros */
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#define SPI_PCS_POL_MASK (0x3F << 12)
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#define SPI_PCS_POL_GET(_in_) (((_in_) & SPI_PCS_POL_MASK) >> 12)
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#define SPI_PCS_POL_SET(_in_) ((_in_) << 12)
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/* Continuous SCK access macros */
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#define SPI_CONT_SCK_MASK (0x1 << 18)
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#define SPI_CONT_SCK_GET(_in_) (((_in_) & SPI_CONT_SCK_MASK) >> 18)
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#define SPI_CONT_SCK_SET(_in_) ((_in_) << 18)
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/* Continuous PCS access macros */
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#define SPI_CONT_PCS_MASK (0x1 << 19)
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#define SPI_CONT_PCS_GET(_in_) (((_in_) & SPI_CONT_PCS_MASK) >> 19)
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#define SPI_CONT_PCS_SET(_in_) ((_in_) << 19)
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/* K64 SPI word/frame size is limited to 16 bits, represented as: (size - 1) */
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#define SPI_K64_WORD_SIZE_MAX (16)
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#endif /* __SPI_K64_H__ */
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