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https://github.com/zephyrproject-rtos/zephyr
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37c13eec7a
RCC device could be common to various STM32 series. Until now, PLL handling code was set in series specific files, even if it was driving the same device than another series. Minimize code duplication by factorizing code between series when possible. With this change, some series get additional features by getting access to code developed for other series. Additionally, while renaming the files, remove the non informative 'x' to minimize file name length Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
28 lines
1.5 KiB
CMake
28 lines
1.5 KiB
CMake
# SPDX-License-Identifier: Apache-2.0
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zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
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zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM clock_control_mcux_ccm.c)
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zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_PCC clock_control_mcux_pcc.c)
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zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c)
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zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF nrf_power_clock.c)
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zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_QUARK_SE quark_se_clock_control.c)
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zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c)
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if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
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if(CONFIG_SOC_SERIES_STM32MP1X)
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zephyr_sources(clock_stm32_ll_mp1.c)
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else()
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zephyr_sources(clock_stm32_ll_common.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X clock_stm32f0_f3.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X clock_stm32f1.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X clock_stm32f2_f4_f7.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X clock_stm32f0_f3.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X clock_stm32f2_f4_f7.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X clock_stm32f2_f4_f7.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0_l1.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_wb.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_wb.c)
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endif()
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endif()
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