mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-07 12:32:58 +00:00
ac74d8b652
Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _DRIVERS_GPIO_CMSDK_AHB_
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#define _DRIVERS_GPIO_CMSDK_AHB_
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#include <gpio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ARM LTD CMSDK AHB General Purpose Input/Output (GPIO) */
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struct gpio_cmsdk_ahb {
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/* Offset: 0x000 (r/w) data register */
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volatile uint32_t data;
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/* Offset: 0x004 (r/w) data output latch register */
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volatile uint32_t dataout;
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volatile uint32_t reserved0[2];
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/* Offset: 0x010 (r/w) output enable set register */
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volatile uint32_t outenableset;
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/* Offset: 0x014 (r/w) output enable clear register */
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volatile uint32_t outenableclr;
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/* Offset: 0x018 (r/w) alternate function set register */
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volatile uint32_t altfuncset;
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/* Offset: 0x01c (r/w) alternate function clear register */
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volatile uint32_t altfuncclr;
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/* Offset: 0x020 (r/w) interrupt enable set register */
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volatile uint32_t intenset;
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/* Offset: 0x024 (r/w) interrupt enable clear register */
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volatile uint32_t intenclr;
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/* Offset: 0x028 (r/w) interrupt type set register */
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volatile uint32_t inttypeset;
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/* Offset: 0x02c (r/w) interrupt type clear register */
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volatile uint32_t inttypeclr;
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/* Offset: 0x030 (r/w) interrupt polarity set register */
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volatile uint32_t intpolset;
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/* Offset: 0x034 (r/w) interrupt polarity clear register */
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volatile uint32_t intpolclr;
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union {
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/* Offset: 0x038 (r/ ) interrupt status register */
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volatile uint32_t intstatus;
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/* Offset: 0x038 ( /w) interrupt clear register */
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volatile uint32_t intclear;
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};
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volatile uint32_t reserved1[241];
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/* Offset: 0x400 - 0x7fc lower byte masked access register (r/w) */
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volatile uint32_t lb_masked[256];
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/* Offset: 0x800 - 0xbfc upper byte masked access register (r/w) */
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volatile uint32_t ub_masked[256];
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVERS_GPIO_CMSDK_AHB_ */
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