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We provide an option for low-memory systems to use a single set of page tables for all threads. This is only supported if KPTI and SMP are disabled. This configuration saves a considerable amount of RAM, especially if multiple memory domains are used, at a cost of context switching overhead. Some caching techniques are used to reduce the amount of context switch updates; the page tables aren't updated if switching to a supervisor thread, and the page table configuration of the last user thread switched in is cached. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> |
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| application_development | ||
| arch | ||
| benchmarks | ||
| bluetooth | ||
| boards | ||
| crypto | ||
| deprecated/inttype | ||
| drivers | ||
| kernel | ||
| lib | ||
| misc/test_build | ||
| net | ||
| portability | ||
| posix | ||
| shell | ||
| subsys | ||
| unit | ||
| ztest | ||