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https://github.com/zephyrproject-rtos/zephyr
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8e4a534ea1
Some kernel operations, like scheduler locking can be optmized out, since coop threads lock the scheduler by their very nature. Also, the interrupt exit path for all architecture does not have to do any rescheduling, again by the nature of non-preemptible threads. Change-Id: I270e926df3ce46e11d77270330f2f4b463971763 Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
257 lines
6.5 KiB
ArmAsm
257 lines
6.5 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Handling of transitions to-and-from regular IRQs (RIRQ)
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*
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* This module implements the code for handling entry to and exit from regular
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* IRQs.
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*
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* See isr_wrapper.S for details.
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*/
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#define _ASMLANGUAGE
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#include <kernel_structs.h>
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <arch/cpu.h>
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#include <swap_macros.h>
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GTEXT(_rirq_enter)
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GTEXT(_rirq_exit)
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GTEXT(_rirq_common_interrupt_swap)
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#if 0 /* TODO: when FIRQ is not present, all would be regular */
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#define NUM_REGULAR_IRQ_PRIO_LEVELS CONFIG_NUM_IRQ_PRIO_LEVELS
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#else
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#define NUM_REGULAR_IRQ_PRIO_LEVELS (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
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#endif
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/* note: the above define assumes that prio 0 IRQ is for FIRQ, and
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* that all others are regular interrupts.
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* TODO: Revist this if FIRQ becomes configurable.
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*/
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#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
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#error "nested regular interrupts are not supported."
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/*
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* Nesting of Regularing interrupts is not yet supported.
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* Set CONFIG_NUM_IRQ_PRIO_LEVELS to 2 even if SOC supports more.
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*/
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#endif
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/**
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*
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* @brief Work to be done before handing control to an IRQ ISR
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*
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* The processor pushes automatically all registers that need to be saved.
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* However, since the processor always runs at kernel privilege there is no
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* automatic switch to the IRQ stack: this must be done in software.
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*
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* Assumption by _isr_demux: r3 is untouched by _rirq_enter.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _rirq_enter)
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mov r1, _kernel
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#ifdef CONFIG_ARC_STACK_CHECKING
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/* disable stack checking */
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lr r2, [_ARC_V2_STATUS32]
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bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
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kflag r2
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#endif
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ld_s r2, [r1, _kernel_offset_to_current]
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#if NUM_REGULAR_IRQ_PRIO_LEVELS == 1
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st sp, [r2, _thread_offset_to_sp]
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ld sp, [r1, _kernel_offset_to_irq_stack]
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#else
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#error regular irq nesting is not implemented
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#endif
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j _isr_demux
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/**
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*
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* @brief Work to be done exiting an IRQ
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _rirq_exit)
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#ifdef CONFIG_PREEMPT_ENABLED
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mov r1, _kernel
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ld_s r2, [r1, _kernel_offset_to_current]
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/*
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* Lock interrupts to ensure kernel queues do not change from this
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* point on until return from interrupt.
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*/
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clri
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#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
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/* check if we're a nested interrupt: if so, let the interrupted interrupt
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* handle the reschedule */
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lr r3, [_ARC_V2_AUX_IRQ_ACT]
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ffs r0, r3
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asl r0, 1, r0
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/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
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* AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is greater
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* than FFS(AUX_IRQ_ACT), it means that another bit is set so an
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* interrupt was interrupted.
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*/
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cmp r0, r3
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brgt _rirq_return_from_rirq
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ld sp, [r2, _thread_offset_to_sp]
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#endif
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/*
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* Both (a)reschedule and (b)non-reschedule cases need to load the current
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* thread's stack, but don't have to use it until the decision is taken:
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* load the delay slots with the 'load stack pointer' instruction.
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*
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* a) needs to load it to save outgoing context.
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* b) needs to load it to restore the interrupted context.
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*/
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/* coop thread ? do not schedule */
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ld_s r0, [r2, _thread_offset_to_prio]
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cmp_s r0, 0
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blt.d _rirq_no_reschedule
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ld sp, [r2, _thread_offset_to_sp]
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/* scheduler locked ? do not schedule */
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ld_s r0, [r2, _thread_offset_to_sched_locked]
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#ifdef CONFIG_ARC_STACK_CHECKING
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brle.d r0, 0, _rirq_reschedule_check
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ld sp, [r2, _thread_offset_to_sp]
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b _rirq_no_reschedule
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/* This branch is a bit far */
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_rirq_reschedule_check:
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#else
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brgt.d r0, 0, _rirq_no_reschedule
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ld sp, [r2, _thread_offset_to_sp]
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#endif
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/* check if the current thread needs to be rescheduled */
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ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
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breq.d r0, r2, _rirq_no_reschedule
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/* delay slot: always load the current thread's stack */
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ld sp, [r2, _thread_offset_to_sp]
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/* cached thread to run is in r0, fall through */
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.balign 4
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_rirq_reschedule:
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/* _save_callee_saved_regs expects outgoing thread in r2 */
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_save_callee_saved_regs
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st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
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/* incoming thread is in r0: it becomes the new 'current' */
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mov r2, r0
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st_s r2, [r1, _kernel_offset_to_current]
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.balign 4
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_rirq_common_interrupt_swap:
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/* r2 contains pointer to new thread */
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#ifdef CONFIG_ARC_STACK_CHECKING
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/* Use stack top and down registers from restored context */
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add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
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sr r3, [_ARC_V2_KSTACK_TOP]
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ld_s r3, [r2, _thread_offset_to_stack_top]
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sr r3, [_ARC_V2_KSTACK_BASE]
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#endif
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/*
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* _load_callee_saved_regs expects incoming thread in r2.
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* _load_callee_saved_regs restores the stack pointer.
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*/
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_load_callee_saved_regs
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ld_s r3, [r2, _thread_offset_to_relinquish_cause]
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breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
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nop
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breq r3, _CAUSE_FIRQ, _rirq_return_from_firq
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nop
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/* fall through */
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.balign 4
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_rirq_return_from_coop:
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/* status32 and pc (blink) are already on the stack in the right order */
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/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
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ld_s r0, [sp, 4]
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ld_s r3, [r2, _thread_offset_to_intlock_key]
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st 0, [r2, _thread_offset_to_intlock_key]
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cmp r3, 0
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or.ne r0, r0, _ARC_V2_STATUS32_IE
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st_s r0, [sp, 4]
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/* carve fake stack */
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/*
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* a) status32/pc are already on the stack
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* b) a real value will be pushed in r0
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*/
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sub sp, sp, (___isf_t_SIZEOF - 12)
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/* push return value on stack */
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ld_s r0, [r2, _thread_offset_to_return_value]
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push_s r0
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/*
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* r13 is part of both the callee and caller-saved register sets because
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* the processor is only able to save registers in pair in the regular
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* IRQ prologue. r13 thus has to be set to its correct value in the IRQ
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* stack frame.
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*/
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st_s r13, [sp, ___isf_t_r13_OFFSET]
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/* stack now has the IRQ stack frame layout, pointing to r0 */
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/* fall through to rtie instruction */
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.balign 4
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_rirq_return_from_firq:
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_rirq_return_from_rirq:
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/* rtie will pop the rest from the stack */
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/* fall through to rtie instruction */
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#endif /* CONFIG_PREEMPT_ENABLED */
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.balign 4
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_rirq_no_reschedule:
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rtie
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