mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-10 22:47:06 +00:00
dff5f6a038
Make the i2c_transfer() to transact messages through the I2C bus. It is useful for I2C storage devices, as now we can send one message containing the destination byte/block address, then send the data in another message. There is no need to construct one continuous data buffer to send both address and data anymore. The drivers and sample apps have been updated to utilize updated API when appropriate. For i2c_dw, only master mode has been updated. Slave mode will be updated once we can adequately test it. Change-Id: I0a811d60567367817fcc8d15f5454e5c933722e2 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Header for I2C driver for Quark SE Sensor Subsystem
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*/
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#ifndef __DRIVERS_I2C_QUARK_SE_SS_H__
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#define __DRIVERS_I2C_QUARK_SE_SS_H__
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#include <i2c.h>
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#include <stdbool.h>
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/* dev->state values from IC_DATA_CMD Data transfer mode settings (bit 8) */
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#define I2C_QSE_SS_STATE_READY (0)
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#define I2C_QSE_SS_CMD_SEND (1 << 0)
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#define I2C_QSE_SS_CMD_RECV (1 << 1)
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#define I2C_QSE_SS_CMD_ERROR (1 << 2)
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#define I2C_QSE_SS_BUSY (1 << 3)
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/*
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* DesignWare speed values don't directly translate from the Zephyr speed
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* selections in include/i2c.h so here we do a little translation
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*/
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#define I2C_QSE_SS_SPEED_STANDARD 0x1
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#define I2C_QSE_SS_SPEED_FAST 0x2
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#define I2C_QSE_SS_SPEED_FAST_PLUS 0x2
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/* IC_CON Low count and high count default values */
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/* TODO verify all values for Quark SE SS */
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#define I2C_STD_HCNT (CONFIG_I2C_CLOCK_SPEED * 4)
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#define I2C_STD_LCNT (CONFIG_I2C_CLOCK_SPEED * 5)
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#define I2C_FS_HCNT ((CONFIG_I2C_CLOCK_SPEED * 6) / 8)
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#define I2C_FS_LCNT ((CONFIG_I2C_CLOCK_SPEED * 7) / 8)
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typedef void (*i2c_qse_ss_cfg_func_t)(struct device *port);
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struct i2c_qse_ss_rom_config {
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uint32_t base_address;
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i2c_qse_ss_cfg_func_t config_func;
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/* IRQ for ERR (error) conditions */
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uint32_t isr_err_vector;
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uint32_t isr_err_mask;
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/* IRQ for RX_AVAIL */
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uint32_t isr_rx_vector;
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uint32_t isr_rx_mask;
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/* IRQ for TX_REQ */
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uint32_t isr_tx_vector;
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uint32_t isr_tx_mask;
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/* IRQ for STOP_DET */
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uint32_t isr_stop_vector;
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uint32_t isr_stop_mask;
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};
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struct i2c_qse_ss_dev_config {
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device_sync_call_t sync;
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union dev_config app_config;
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volatile uint8_t state; /* last direction of transfer */
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uint8_t xfr_flags;
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uint8_t *xfr_buf;
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uint32_t xfr_len;
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uint32_t request_bytes;
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uint16_t hcnt;
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uint16_t lcnt;
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};
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#endif /* __DRIVERS_I2C_QUARK_SE_SS_H__ */
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