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https://github.com/zephyrproject-rtos/zephyr
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07160fa153
SPARC is an open and royalty free processor architecture. This commit provides SPARC architecture support to Zephyr. It is compatible with the SPARC V8 specification and the SPARC ABI and is independent of processor implementation. Functionality specific to SPRAC processor implementations should go in soc/sparc. One example is the LEON3 SOC which is part of this patch set. The architecture port is fully SPARC ABI compatible, including trap handlers and interrupt context. Number of implemented register windows can be configured. Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic instructions from SPARC V9. An option has been defined in the architecture port to forward the corresponding code-generation option to the compiler. Stack size related config options have been defined in sparc/Kconfig to match the SPARC ABI. Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com> Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
37 lines
882 B
C
37 lines
882 B
C
/* cpu.h - automatically selects the correct arch.h file to include */
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/*
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* Copyright (c) 1997-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_CPU_H_
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#define ZEPHYR_INCLUDE_ARCH_CPU_H_
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#include <sys/arch_interface.h>
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#if defined(CONFIG_X86)
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#include <arch/x86/arch.h>
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#elif defined(CONFIG_ARM64)
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#include <arch/arm/aarch64/arch.h>
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#elif defined(CONFIG_ARM)
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#include <arch/arm/aarch32/arch.h>
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#elif defined(CONFIG_ARC)
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#include <arch/arc/arch.h>
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#elif defined(CONFIG_NIOS2)
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#include <arch/nios2/arch.h>
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#elif defined(CONFIG_RISCV)
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#include <arch/riscv/arch.h>
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#elif defined(CONFIG_XTENSA)
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#include <arch/xtensa/arch.h>
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#elif defined(CONFIG_ARCH_POSIX)
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#include <arch/posix/arch.h>
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#elif defined(CONFIG_SPARC)
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#include <arch/sparc/arch.h>
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#else
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#error "Unknown Architecture"
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_CPU_H_ */
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