mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-23 03:36:06 +00:00
8974c248cf
Use the RTIO work queue to fake the i2c submit calls for drivers which haven't yet implemented the API. Applications can change the size of the work queue pool depending on how much traffic they have on the buses. Signed-off-by: Yuval Peress <peress@google.com>
482 lines
15 KiB
C
482 lines
15 KiB
C
/*
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* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief I2C driver for Infineon XMC MCU family.
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*/
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#define DT_DRV_COMPAT infineon_xmc4xxx_i2c
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(i2c_infineon_xmc4, CONFIG_I2C_LOG_LEVEL);
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/drivers/pinctrl.h>
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#include "i2c-priv.h"
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#include <xmc_i2c.h>
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#include <xmc_usic.h>
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#define USIC_IRQ_MIN 84
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#define IRQS_PER_USIC 6
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#define I2C_XMC_EVENTS_MASK ( \
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XMC_I2C_CH_EVENT_RECEIVE_START | \
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XMC_I2C_CH_EVENT_DATA_LOST | \
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XMC_I2C_CH_EVENT_TRANSMIT_SHIFT | \
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XMC_I2C_CH_EVENT_TRANSMIT_BUFFER | \
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XMC_I2C_CH_EVENT_STANDARD_RECEIVE | \
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XMC_I2C_CH_EVENT_ALTERNATIVE_RECEIVE | \
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XMC_I2C_CH_EVENT_BAUD_RATE_GENERATOR | \
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XMC_I2C_CH_EVENT_START_CONDITION_RECEIVED | \
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XMC_I2C_CH_EVENT_REPEATED_START_CONDITION_RECEIVED | \
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XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED | \
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XMC_I2C_CH_EVENT_NACK | \
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XMC_I2C_CH_EVENT_ARBITRATION_LOST | \
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XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST | \
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XMC_I2C_CH_EVENT_ERROR | \
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XMC_I2C_CH_EVENT_ACK)
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#define I2C_XMC_STATUS_FLAG_ERROR_MASK ( \
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XMC_I2C_CH_STATUS_FLAG_WRONG_TDF_CODE_FOUND | \
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XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED | \
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XMC_I2C_CH_STATUS_FLAG_ARBITRATION_LOST | \
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XMC_I2C_CH_STATUS_FLAG_ERROR | \
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XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION)
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/* I2C speed */
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#define XMC4_I2C_SPEED_STANDARD (100000UL)
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#define XMC4_I2C_SPEED_FAST (400000UL)
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/* Data structure */
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struct ifx_xmc4_i2c_data {
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XMC_I2C_CH_CONFIG_t cfg;
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struct k_sem operation_sem;
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struct k_sem target_sem;
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struct i2c_target_config *p_target_config;
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uint32_t dev_config;
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uint8_t target_wr_byte;
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uint8_t target_wr_buffer[CONFIG_I2C_INFINEON_XMC4_TARGET_BUF];
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bool ignore_slave_select;
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bool is_configured;
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};
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/* Device config structure */
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struct ifx_xmc4_i2c_config {
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XMC_USIC_CH_t *i2c;
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const struct pinctrl_dev_config *pcfg;
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uint8_t scl_src;
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uint8_t sda_src;
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uint32_t bitrate;
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void (*irq_config_func)(const struct device *dev);
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};
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static int ifx_xmc4_i2c_configure(const struct device *dev, uint32_t dev_config)
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{
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struct ifx_xmc4_i2c_data *data = dev->data;
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const struct ifx_xmc4_i2c_config *config = dev->config;
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/* This is deprecated and could be ignored in the future */
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if (dev_config & I2C_ADDR_10_BITS) {
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LOG_ERR("Use I2C_MSG_ADDR_10_BITS instead of I2C_ADDR_10_BITS");
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return -EIO;
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}
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switch (I2C_SPEED_GET(dev_config)) {
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case I2C_SPEED_STANDARD:
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data->cfg.baudrate = XMC4_I2C_SPEED_STANDARD;
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break;
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case I2C_SPEED_FAST:
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data->cfg.baudrate = XMC4_I2C_SPEED_FAST;
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break;
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default:
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LOG_ERR("Unsupported speed");
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return -ERANGE;
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}
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data->dev_config = dev_config;
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/* Acquire semaphore (block I2C operation for another thread) */
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if (k_sem_take(&data->operation_sem, K_FOREVER)) {
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return -EIO;
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}
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XMC_I2C_CH_Stop(config->i2c);
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/* Configure the I2C resource */
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data->cfg.normal_divider_mode = false;
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XMC_I2C_CH_Init(config->i2c, &data->cfg);
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XMC_I2C_CH_SetInputSource(config->i2c, XMC_I2C_CH_INPUT_SCL, config->scl_src);
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XMC_I2C_CH_SetInputSource(config->i2c, XMC_I2C_CH_INPUT_SDA, config->sda_src);
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if (data->dev_config & I2C_MODE_CONTROLLER) {
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XMC_USIC_CH_SetFractionalDivider(config->i2c,
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XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL,
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1023U);
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} else {
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config->irq_config_func(dev);
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}
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XMC_I2C_CH_Start(config->i2c);
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data->is_configured = true;
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/* Release semaphore */
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k_sem_give(&data->operation_sem);
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return 0;
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}
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static int ifx_xmc4_i2c_get_config(const struct device *dev, uint32_t *dev_config)
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{
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struct ifx_xmc4_i2c_data *data = dev->data;
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const struct ifx_xmc4_i2c_config *config = dev->config;
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if (!data->is_configured) {
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/* if not yet configured return configuration that will be used */
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/* when transfer() is called */
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uint32_t bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
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*dev_config = I2C_MODE_CONTROLLER | bitrate_cfg;
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return 0;
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}
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*dev_config = data->dev_config;
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return 0;
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}
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static int ifx_xmc4_i2c_msg_validate(struct i2c_msg *msg, uint8_t num_msgs)
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{
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for (uint32_t i = 0u; i < num_msgs; i++) {
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if ((I2C_MSG_ADDR_10_BITS & msg[i].flags) || (msg[i].buf == NULL)) {
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return -EINVAL;
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}
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}
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return 0;
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}
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static int ifx_xmc4_i2c_transfer(const struct device *dev, struct i2c_msg *msg, uint8_t num_msgs,
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uint16_t addr)
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{
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struct ifx_xmc4_i2c_data *data = dev->data;
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const struct ifx_xmc4_i2c_config *config = dev->config;
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XMC_I2C_CH_CMD_t cmd_type;
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if (!num_msgs) {
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return 0;
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}
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if (!data->is_configured) {
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int ret;
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uint32_t bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
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ret = ifx_xmc4_i2c_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
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if (ret) {
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return ret;
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}
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}
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/* Acquire semaphore (block I2C transfer for another thread) */
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if (k_sem_take(&data->operation_sem, K_FOREVER)) {
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return -EIO;
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}
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/* This function checks if msg.buf is not NULL and if target address is not 10 bit. */
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if (ifx_xmc4_i2c_msg_validate(msg, num_msgs) != 0) {
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k_sem_give(&data->operation_sem);
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return -EINVAL;
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}
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for (uint32_t msg_index = 0u; msg_index < num_msgs; msg_index++) {
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XMC_I2C_CH_ClearStatusFlag(config->i2c, 0xFFFFFFFF);
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if ((msg_index == 0) || (msg[msg_index].flags & I2C_MSG_RESTART)) {
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/* Send START condition */
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cmd_type = ((msg[msg_index].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) ?
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XMC_I2C_CH_CMD_READ : XMC_I2C_CH_CMD_WRITE;
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if (msg[msg_index].flags & I2C_MSG_RESTART) {
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XMC_I2C_CH_MasterRepeatedStart(config->i2c, addr << 1, cmd_type);
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} else {
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XMC_I2C_CH_MasterStart(config->i2c, addr << 1, cmd_type);
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}
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/* Wait for acknowledge */
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while ((XMC_I2C_CH_GetStatusFlag(config->i2c) &
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XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED) == 0U) {
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/* wait for ACK from slave */
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if (XMC_I2C_CH_GetStatusFlag(config->i2c) &
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I2C_XMC_STATUS_FLAG_ERROR_MASK) {
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k_sem_give(&data->operation_sem);
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return -EIO;
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}
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}
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XMC_I2C_CH_ClearStatusFlag(config->i2c,
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XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED);
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}
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for (uint32_t buf_index = 0u; buf_index < msg[msg_index].len; buf_index++) {
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if (cmd_type == XMC_I2C_CH_CMD_WRITE) {
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/* Transmit next command from I2C master to I2C slave */
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XMC_I2C_CH_MasterTransmit(config->i2c,
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msg[msg_index].buf[buf_index]);
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/* Wait for acknowledge */
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while ((XMC_I2C_CH_GetStatusFlag(config->i2c) &
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XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED) == 0U) {
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/* wait for ACK from slave */
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if (XMC_I2C_CH_GetStatusFlag(config->i2c) &
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I2C_XMC_STATUS_FLAG_ERROR_MASK) {
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k_sem_give(&data->operation_sem);
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return -EIO;
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}
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}
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XMC_I2C_CH_ClearStatusFlag(config->i2c,
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XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED);
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/* Wait until TX FIFO is empty */
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while (!XMC_USIC_CH_TXFIFO_IsEmpty(config->i2c)) {
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/* wait until all data is sent by HW */
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if (XMC_I2C_CH_GetStatusFlag(config->i2c) &
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I2C_XMC_STATUS_FLAG_ERROR_MASK) {
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k_sem_give(&data->operation_sem);
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return -EIO;
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}
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}
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} else {
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if (buf_index == (msg[msg_index].len - 1)) {
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XMC_I2C_CH_MasterReceiveNack(config->i2c);
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} else {
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XMC_I2C_CH_MasterReceiveAck(config->i2c);
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}
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while ((XMC_I2C_CH_GetStatusFlag(config->i2c) &
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(XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION |
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XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION)) == 0U) {
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/* wait for data byte from slave */
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if (XMC_I2C_CH_GetStatusFlag(config->i2c) &
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I2C_XMC_STATUS_FLAG_ERROR_MASK) {
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k_sem_give(&data->operation_sem);
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return -EIO;
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}
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}
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XMC_I2C_CH_ClearStatusFlag(config->i2c,
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XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION |
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XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION);
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msg[msg_index].buf[buf_index] =
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XMC_I2C_CH_GetReceivedData(config->i2c);
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}
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}
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/* Send STOP condition */
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if (msg[msg_index].flags & I2C_MSG_STOP) {
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XMC_I2C_CH_MasterStop(config->i2c);
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}
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}
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/* Release semaphore (After I2C transfer is complete) */
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k_sem_give(&data->operation_sem);
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return 0;
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}
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static int ifx_xmc4_i2c_init(const struct device *dev)
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{
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struct ifx_xmc4_i2c_data *data = dev->data;
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const struct ifx_xmc4_i2c_config *config = dev->config;
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int ret;
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/* Configure semaphores */
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ret = k_sem_init(&data->operation_sem, 1, 1);
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if (ret) {
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return ret;
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}
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ret = k_sem_init(&data->target_sem, 1, 1);
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if (ret) {
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return ret;
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}
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/* Configure dt provided device signals when available */
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return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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}
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static int ifx_xmc4_i2c_target_register(const struct device *dev, struct i2c_target_config *cfg)
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{
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struct ifx_xmc4_i2c_data *data = dev->data;
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const struct ifx_xmc4_i2c_config *config = dev->config;
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uint32_t bitrate_cfg;
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if (!cfg ||
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!cfg->callbacks->read_requested ||
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!cfg->callbacks->read_processed ||
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!cfg->callbacks->write_requested ||
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!cfg->callbacks->write_received ||
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!cfg->callbacks->stop) {
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return -EINVAL;
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}
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if (cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) {
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return -ENOTSUP;
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}
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/* Acquire semaphore (block I2C operation for another thread) */
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if (k_sem_take(&data->target_sem, K_FOREVER)) {
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return -EIO;
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}
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data->p_target_config = cfg;
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data->cfg.address = cfg->address << 1;
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if (data->is_configured) {
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uint32_t bitrate;
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bitrate = I2C_SPEED_GET(data->dev_config);
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bitrate_cfg = i2c_map_dt_bitrate(bitrate);
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} else {
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bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
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}
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if (ifx_xmc4_i2c_configure(dev, bitrate_cfg) != 0) {
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/* Release semaphore */
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k_sem_give(&data->target_sem);
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return -EIO;
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}
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k_sem_give(&data->target_sem);
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return 0;
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}
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static int ifx_xmc4_i2c_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
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{
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struct ifx_xmc4_i2c_data *data = dev->data;
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const struct ifx_xmc4_i2c_config *config = dev->config;
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/* Acquire semaphore (block I2C operation for another thread) */
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if (k_sem_take(&data->operation_sem, K_FOREVER)) {
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return -EIO;
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}
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data->p_target_config = NULL;
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XMC_I2C_CH_DisableEvent(config->i2c, I2C_XMC_EVENTS_MASK);
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/* Release semaphore */
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k_sem_give(&data->operation_sem);
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return 0;
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}
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static void i2c_xmc4_isr(const struct device *dev)
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{
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struct ifx_xmc4_i2c_data *data = dev->data;
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const struct ifx_xmc4_i2c_config *config = dev->config;
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const struct i2c_target_callbacks *callbacks = data->p_target_config->callbacks;
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uint32_t status = XMC_I2C_CH_GetStatusFlag(config->i2c);
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while (status) {
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XMC_I2C_CH_ClearStatusFlag(config->i2c, status);
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if (status & XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED) {
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/* Flush the TX buffer */
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XMC_USIC_CH_SetTransmitBufferStatus(config->i2c,
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XMC_USIC_CH_TBUF_STATUS_SET_IDLE);
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callbacks->stop(data->p_target_config);
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break;
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}
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if (!data->ignore_slave_select && (status & XMC_I2C_CH_STATUS_FLAG_SLAVE_SELECT)) {
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data->ignore_slave_select = true;
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/* Start a slave read */
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if (status & XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED) {
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callbacks->read_requested(data->p_target_config,
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&data->target_wr_byte);
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XMC_I2C_CH_SlaveTransmit(config->i2c, data->target_wr_byte);
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} else {
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callbacks->write_requested(data->p_target_config);
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}
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}
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/* Continue a slave read */
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if (status & XMC_I2C_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION) {
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callbacks->read_processed(data->p_target_config, &data->target_wr_byte);
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XMC_I2C_CH_SlaveTransmit(config->i2c, data->target_wr_byte);
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}
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/* Start/Continue a slave write */
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if (status & (XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION |
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XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION)) {
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callbacks->write_received(data->p_target_config,
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XMC_I2C_CH_GetReceivedData(config->i2c));
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}
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if ((status & XMC_I2C_CH_STATUS_FLAG_START_CONDITION_RECEIVED) ||
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(status & XMC_I2C_CH_STATUS_FLAG_REPEATED_START_CONDITION_RECEIVED)) {
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data->ignore_slave_select = false;
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}
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status = XMC_I2C_CH_GetStatusFlag(config->i2c);
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}
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}
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/* I2C API structure */
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static const struct i2c_driver_api i2c_xmc4_driver_api = {
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.configure = ifx_xmc4_i2c_configure,
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.transfer = ifx_xmc4_i2c_transfer,
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.get_config = ifx_xmc4_i2c_get_config,
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.target_register = ifx_xmc4_i2c_target_register,
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.target_unregister = ifx_xmc4_i2c_target_unregister,
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#ifdef CONFIG_I2C_RTIO
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.iodev_submit = i2c_iodev_submit_fallback,
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#endif
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};
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/* Macros for I2C instance declaration */
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#define XMC4_IRQ_HANDLER_INIT(index) \
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static void i2c_xmc4_irq_setup_##index(const struct device *dev) \
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{ \
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const struct ifx_xmc4_i2c_config *config = dev->config; \
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uint8_t irq_num = DT_INST_IRQN(index); \
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uint8_t service_request = (irq_num - USIC_IRQ_MIN) % IRQS_PER_USIC; \
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\
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XMC_I2C_CH_SelectInterruptNodePointer(config->i2c, \
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XMC_I2C_CH_INTERRUPT_NODE_POINTER_RECEIVE, service_request); \
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XMC_I2C_CH_SelectInterruptNodePointer(config->i2c, \
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XMC_I2C_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, service_request); \
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\
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XMC_I2C_CH_EnableEvent(config->i2c, I2C_XMC_EVENTS_MASK); \
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\
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IRQ_CONNECT(DT_INST_IRQN(index), DT_INST_IRQ(index, priority), i2c_xmc4_isr, \
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DEVICE_DT_INST_GET(index), 0); \
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\
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irq_enable(irq_num); \
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}
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#define XMC4_IRQ_HANDLER_STRUCT_INIT(index) .irq_config_func = i2c_xmc4_irq_setup_##index
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#define INFINEON_XMC4_I2C_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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XMC4_IRQ_HANDLER_INIT(n) \
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\
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static struct ifx_xmc4_i2c_data ifx_xmc4_i2c_data##n; \
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\
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static const struct ifx_xmc4_i2c_config i2c_xmc4_cfg_##n = { \
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.i2c = (XMC_USIC_CH_t *)DT_INST_REG_ADDR(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.scl_src = DT_INST_ENUM_IDX(n, scl_src), \
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.sda_src = DT_INST_ENUM_IDX(n, sda_src), \
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.bitrate = DT_INST_PROP_OR(n, clock_frequency, I2C_SPEED_STANDARD), \
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XMC4_IRQ_HANDLER_STRUCT_INIT(n) \
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}; \
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\
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I2C_DEVICE_DT_INST_DEFINE(n, ifx_xmc4_i2c_init, NULL, &ifx_xmc4_i2c_data##n, \
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&i2c_xmc4_cfg_##n, POST_KERNEL, \
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CONFIG_I2C_INIT_PRIORITY, &i2c_xmc4_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(INFINEON_XMC4_I2C_INIT)
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