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https://github.com/zephyrproject-rtos/zephyr
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The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows the riscv PLIC specification as defined in the riscv privilege architecture specification. It provides implementation for the riscv PLIC APIs as required by the riscv-privilege SOC Family for SOCs providing support for the RISCV_HAS_PLIC config. Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
13 lines
360 B
Makefile
13 lines
360 B
Makefile
obj-${CONFIG_PIC_DISABLE} = i8259.o
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obj-$(CONFIG_MVIC) += mvic.o
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obj-$(CONFIG_LOAPIC) += loapic_intr.o system_apic.o
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obj-$(CONFIG_IOAPIC) += ioapic_intr.o
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obj-$(CONFIG_LOAPIC_SPURIOUS_VECTOR) += loapic_spurious.o
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obj-$(CONFIG_ARCV2_INTERRUPT_UNIT) += arcv2_irq_unit.o
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obj-$(CONFIG_SOC_FAMILY_STM32) += exti_stm32.o
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obj-$(CONFIG_PLIC_FE310) += plic_fe310.o
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