mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-07 07:45:22 +00:00
ccad5bf3e3
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
77 lines
1.3 KiB
C
77 lines
1.3 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32_IWDG_H_
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#define _STM32_IWDG_H_
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#include <zephyr/types.h>
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/**
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* @brief Driver for Independent Watchdog (IWDG) for STM32 MCUs
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 19: Independent watchdog (IWDG)
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*
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*/
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/* counter reload trigger */
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#define STM32_IWDG_KR_RELOAD 0xaaaa
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/* magic value for unlocking write access to PR and RLR */
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#define STM32_IWDG_KR_UNLOCK 0x5555
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/* watchdog start */
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#define STM32_IWDG_KR_START 0xcccc
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/* 19.4.1 IWDG_KR */
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union __iwdg_kr {
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u32_t val;
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struct {
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u16_t key;
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u16_t rsvd;
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} bit;
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};
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/* 19.4.2 IWDG_PR */
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union __iwdg_pr {
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u32_t val;
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struct {
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u32_t pr :3 __packed;
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u32_t rsvd__3_31 :29 __packed;
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} bit;
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};
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/* 19.4.3 IWDG_RLR */
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union __iwdg_rlr {
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u32_t val;
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struct {
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u32_t rl :12 __packed;
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u32_t rsvd__12_31 :20 __packed;
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} bit;
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};
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/* 19.4.4 IWDG_SR */
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union __iwdg_sr {
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u32_t val;
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struct {
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u32_t pvu :1 __packed;
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u32_t rvu :1 __packed;
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u32_t rsvd__2_31 :30 __packed;
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} bit;
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};
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/* 19.4.5 IWDG register map */
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struct iwdg_stm32 {
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union __iwdg_kr kr;
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union __iwdg_pr pr;
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union __iwdg_rlr rlr;
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union __iwdg_sr sr;
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};
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#endif /* _STM32_IWDG_H_ */
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