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zephyr/soc/xtensa
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Mohamed ElShahawi f9e0fa9af3 drivers: esp32/clock_control: support UART, I2C 
- Change default CPU Clock to 240MHz
(PLL is activated)
- I2C, UART will use sysclk from clock driver
- esp32_enable_peripheral replaced by
clock_control_on

Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
2020-06-16 09:00:51 -05:00
..
esp32 drivers: esp32/clock_control: support UART, I2C 2020-06-16 09:00:51 -05:00
intel_apl_adsp zephyr: replace zephyr integer types with C99 types 2020-06-08 08:23:57 -05:00
intel_s1000 zephyr: replace zephyr integer types with C99 types 2020-06-08 08:23:57 -05:00
sample_controller arch: xtensa: replace DT_CPU_CLOCK_FREQUENCY with new dt macros 2020-04-22 11:38:33 -05:00