mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-14 23:41:56 +00:00
0906a51dac
Commit aad21ecb31 introduced an incorrect
pattern of handling ADC sampling requests with invalid parameters in
both nRF ADC drivers. After discarding such request, the drivers do not
release properly the access lock and therefore become unusable.
Unfortunately, this pattern were later on copied in all other ADC
drivers in the source tree.
This commit adds the proper lock releasing in all the affected drivers.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
331 lines
8.3 KiB
C
331 lines
8.3 KiB
C
/*
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* Copyright (c) 2017-2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <adc.h>
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#include <fsl_adc16.h>
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(adc_mcux_adc16);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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struct mcux_adc16_config {
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ADC_Type *base;
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void (*irq_config_func)(struct device *dev);
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};
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struct mcux_adc16_data {
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struct device *dev;
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struct adc_context ctx;
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u16_t *buffer;
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u16_t *repeat_buffer;
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u32_t channels;
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u8_t channel_id;
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};
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static int mcux_adc16_channel_setup(struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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u8_t channel_id = channel_cfg->channel_id;
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if (channel_id > (ADC_SC1_ADCH_MASK >> ADC_SC1_ADCH_SHIFT)) {
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LOG_ERR("Channel %d is not valid", channel_id);
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return -EINVAL;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Invalid channel acquisition time");
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return -EINVAL;
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}
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if (channel_cfg->differential) {
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LOG_ERR("Differential channels are not supported");
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return -EINVAL;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Invalid channel gain");
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return -EINVAL;
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}
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if (channel_cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Invalid channel reference");
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return -EINVAL;
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}
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return 0;
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}
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static int start_read(struct device *dev, const struct adc_sequence *sequence)
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{
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const struct mcux_adc16_config *config = dev->config->config_info;
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struct mcux_adc16_data *data = dev->driver_data;
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adc16_hardware_average_mode_t mode;
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adc16_resolution_t resolution;
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int error;
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u32_t tmp32;
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ADC_Type *base = config->base;
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switch (sequence->resolution) {
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case 8:
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case 9:
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resolution = kADC16_Resolution8or9Bit;
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break;
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case 10:
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case 11:
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resolution = kADC16_Resolution10or11Bit;
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break;
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case 12:
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case 13:
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resolution = kADC16_Resolution12or13Bit;
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break;
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#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
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case 16:
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resolution = kADC16_Resolution16Bit;
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break;
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#endif
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default:
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LOG_ERR("Invalid resolution");
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return -EINVAL;
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}
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tmp32 = base->CFG1 & ~(ADC_CFG1_MODE_MASK);
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tmp32 |= ADC_CFG1_MODE(resolution);
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base->CFG1 = tmp32;
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switch (sequence->oversampling) {
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case 0:
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mode = kADC16_HardwareAverageDisabled;
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break;
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case 2:
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mode = kADC16_HardwareAverageCount4;
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break;
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case 3:
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mode = kADC16_HardwareAverageCount8;
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break;
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case 4:
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mode = kADC16_HardwareAverageCount16;
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break;
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case 5:
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mode = kADC16_HardwareAverageCount32;
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break;
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default:
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LOG_ERR("Invalid oversampling");
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return -EINVAL;
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}
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ADC16_SetHardwareAverage(config->base, mode);
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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error = adc_context_wait_for_completion(&data->ctx);
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return error;
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}
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static int mcux_adc16_read(struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct mcux_adc16_data *data = dev->driver_data;
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int error;
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adc_context_lock(&data->ctx, false, NULL);
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error = start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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#ifdef CONFIG_ADC_ASYNC
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static int mcux_adc16_read_async(struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct mcux_adc16_data *data = dev->driver_data;
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int error;
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adc_context_lock(&data->ctx, true, async);
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error = start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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#endif
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static void mcux_adc16_start_channel(struct device *dev)
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{
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const struct mcux_adc16_config *config = dev->config->config_info;
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struct mcux_adc16_data *data = dev->driver_data;
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adc16_channel_config_t channel_config;
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u32_t channel_group = 0U;
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data->channel_id = find_lsb_set(data->channels) - 1;
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LOG_DBG("Starting channel %d", data->channel_id);
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#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
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channel_config.enableDifferentialConversion = false;
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#endif
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channel_config.enableInterruptOnConversionCompleted = true;
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channel_config.channelNumber = data->channel_id;
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ADC16_SetChannelConfig(config->base, channel_group, &channel_config);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct mcux_adc16_data *data =
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CONTAINER_OF(ctx, struct mcux_adc16_data, ctx);
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data->channels = ctx->sequence->channels;
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data->repeat_buffer = data->buffer;
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mcux_adc16_start_channel(data->dev);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct mcux_adc16_data *data =
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CONTAINER_OF(ctx, struct mcux_adc16_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static void mcux_adc16_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct mcux_adc16_config *config = dev->config->config_info;
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struct mcux_adc16_data *data = dev->driver_data;
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ADC_Type *base = config->base;
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u32_t channel_group = 0U;
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u16_t result;
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result = ADC16_GetChannelConversionValue(base, channel_group);
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LOG_DBG("Finished channel %d. Result is 0x%04x",
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data->channel_id, result);
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*data->buffer++ = result;
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data->channels &= ~BIT(data->channel_id);
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if (data->channels) {
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mcux_adc16_start_channel(dev);
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} else {
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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static int mcux_adc16_init(struct device *dev)
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{
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const struct mcux_adc16_config *config = dev->config->config_info;
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struct mcux_adc16_data *data = dev->driver_data;
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ADC_Type *base = config->base;
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adc16_config_t adc_config;
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ADC16_GetDefaultConfig(&adc_config);
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#if CONFIG_ADC_MCUX_ADC16_VREF_DEFAULT
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adc_config.referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
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#else /* CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE */
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adc_config.referenceVoltageSource = kADC16_ReferenceVoltageSourceValt;
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#endif
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#if CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_1
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adc_config.clockDivider = kADC16_ClockDivider1;
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#elif CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_2
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adc_config.clockDivider = kADC16_ClockDivider2;
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#elif CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_4
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adc_config.clockDivider = kADC16_ClockDivider4;
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#else /* CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_8 */
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adc_config.clockDivider = kADC16_ClockDivider8;
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#endif
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ADC16_Init(base, &adc_config);
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#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && \
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FSL_FEATURE_ADC16_HAS_CALIBRATION
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ADC16_SetHardwareAverage(base, kADC16_HardwareAverageCount32);
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ADC16_DoAutoCalibration(base);
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#endif
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ADC16_EnableHardwareTrigger(base, false);
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config->irq_config_func(dev);
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data->dev = dev;
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct adc_driver_api mcux_adc16_driver_api = {
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.channel_setup = mcux_adc16_channel_setup,
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.read = mcux_adc16_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = mcux_adc16_read_async,
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#endif
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};
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#if CONFIG_ADC_0
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static void mcux_adc16_config_func_0(struct device *dev);
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static const struct mcux_adc16_config mcux_adc16_config_0 = {
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.base = (ADC_Type *)DT_ADC_0_BASE_ADDRESS,
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.irq_config_func = mcux_adc16_config_func_0,
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};
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static struct mcux_adc16_data mcux_adc16_data_0 = {
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ADC_CONTEXT_INIT_TIMER(mcux_adc16_data_0, ctx),
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ADC_CONTEXT_INIT_LOCK(mcux_adc16_data_0, ctx),
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ADC_CONTEXT_INIT_SYNC(mcux_adc16_data_0, ctx),
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};
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DEVICE_AND_API_INIT(mcux_adc16_0, DT_ADC_0_NAME, &mcux_adc16_init,
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&mcux_adc16_data_0, &mcux_adc16_config_0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&mcux_adc16_driver_api);
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static void mcux_adc16_config_func_0(struct device *dev)
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{
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IRQ_CONNECT(DT_ADC_0_IRQ, DT_ADC_0_IRQ_PRI,
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mcux_adc16_isr, DEVICE_GET(mcux_adc16_0), 0);
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irq_enable(DT_ADC_0_IRQ);
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}
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#endif /* CONFIG_ADC_0 */
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#if CONFIG_ADC_1
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static void mcux_adc16_config_func_1(struct device *dev);
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static const struct mcux_adc16_config mcux_adc16_config_1 = {
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.base = (ADC_Type *)DT_ADC_1_BASE_ADDRESS,
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.irq_config_func = mcux_adc16_config_func_1,
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};
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static struct mcux_adc16_data mcux_adc16_data_1 = {
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ADC_CONTEXT_INIT_TIMER(mcux_adc16_data_1, ctx),
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ADC_CONTEXT_INIT_LOCK(mcux_adc16_data_1, ctx),
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ADC_CONTEXT_INIT_SYNC(mcux_adc16_data_1, ctx),
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};
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DEVICE_AND_API_INIT(mcux_adc16_1, DT_ADC_1_NAME, &mcux_adc16_init,
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&mcux_adc16_data_1, &mcux_adc16_config_1,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&mcux_adc16_driver_api);
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static void mcux_adc16_config_func_1(struct device *dev)
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{
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IRQ_CONNECT(DT_ADC_1_IRQ, DT_ADC_1_IRQ_PRI,
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mcux_adc16_isr, DEVICE_GET(mcux_adc16_1), 0);
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irq_enable(DT_ADC_1_IRQ);
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}
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#endif /* CONFIG_ADC_1 */
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