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41bcac3f1c
The Cortex-M0(+) and in general processors that support only the ARMv6-M instruction set can only access the NVIC_IPRn registers with word accesses, and not with byte ones like the Cortex-M3 and onwards. This patch addresses the issue by modifying the way that _NvicIrqPrioSet() writes to the IPRn register, using a word access for Cortex-M0(+). A similar issue is addressed for internal exceptions, this time for the SHPR registers that are accessed differently on ARMv6-M. Reference code taken from CMSIS. Jira: ZEP-1497 Change-id: I08e1bf60b3b70579b42f4ab926ee835c18bb65bb Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no> Signed-off-by: Kumar Gala <kumar.gala@linaro.org> |
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| arm | ||
| nios2 | ||
| x86 | ||
| cpu.h | ||