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https://github.com/zephyrproject-rtos/zephyr
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60644a3e2c
define the irq handler in case of DMA V1 or V2, for the stm32x soc series with DMA V1 raise Fifo Error if enabled with V2, handle the Global Interrupt Signed-off-by: Francois Ramu <francois.ramu@st.com> Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
216 lines
5.0 KiB
C
216 lines
5.0 KiB
C
/*
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* Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief DMA low level driver implementation for F0/F1/F3/L0/L4 series SoCs.
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*/
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#include <drivers/dma.h>
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#include <soc.h>
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#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(dma_stm32_v2);
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u32_t table_ll_stream[] = {
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LL_DMA_CHANNEL_1,
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LL_DMA_CHANNEL_2,
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LL_DMA_CHANNEL_3,
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LL_DMA_CHANNEL_4,
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LL_DMA_CHANNEL_5,
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#if defined(LL_DMA_CHANNEL_6)
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LL_DMA_CHANNEL_6,
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#endif /* LL_DMA_CHANNEL_6 */
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#if defined(LL_DMA_CHANNEL_7)
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LL_DMA_CHANNEL_7,
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#endif /* LL_DMA_CHANNEL_7 */
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#if defined(LL_DMA_CHANNEL_8)
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LL_DMA_CHANNEL_8,
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#endif
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};
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void (*func_ll_clear_ht[])(DMA_TypeDef *DMAx) = {
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LL_DMA_ClearFlag_HT1,
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LL_DMA_ClearFlag_HT2,
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LL_DMA_ClearFlag_HT3,
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LL_DMA_ClearFlag_HT4,
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LL_DMA_ClearFlag_HT5,
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#if defined(LL_DMA_IFCR_CHTIF6)
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LL_DMA_ClearFlag_HT6,
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#endif /* LL_DMA_IFCR_CHTIF6 */
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#if defined(LL_DMA_IFCR_CHTIF7)
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LL_DMA_ClearFlag_HT7,
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#endif /* LL_DMA_IFCR_CHTIF7 */
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#if defined(LL_DMA_IFCR_CHTIF8)
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LL_DMA_ClearFlag_HT8,
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#endif /* LL_DMA_IFCR_CHTIF8 */
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};
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void (*func_ll_clear_tc[])(DMA_TypeDef *DMAx) = {
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LL_DMA_ClearFlag_TC1,
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LL_DMA_ClearFlag_TC2,
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LL_DMA_ClearFlag_TC3,
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LL_DMA_ClearFlag_TC4,
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LL_DMA_ClearFlag_TC5,
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#if defined(LL_DMA_IFCR_CTCIF6)
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LL_DMA_ClearFlag_TC6,
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#endif /* LL_DMA_IFCR_CTCIF6 */
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#if defined(LL_DMA_IFCR_CTCIF7)
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LL_DMA_ClearFlag_TC7,
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#endif /* LL_DMA_IFCR_CTCIF7 */
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#if defined(LL_DMA_IFCR_CTCIF8)
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LL_DMA_ClearFlag_TC8,
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#endif /* LL_DMA_IFCR_CTCIF8 */
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};
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u32_t (*func_ll_is_active_ht[])(DMA_TypeDef *DMAx) = {
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LL_DMA_IsActiveFlag_HT1,
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LL_DMA_IsActiveFlag_HT2,
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LL_DMA_IsActiveFlag_HT3,
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LL_DMA_IsActiveFlag_HT4,
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LL_DMA_IsActiveFlag_HT5,
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#if defined(LL_DMA_ISR_HTIF6)
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LL_DMA_IsActiveFlag_HT6,
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#endif /* LL_DMA_ISR_HTIF6 */
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#if defined(LL_DMA_ISR_HTIF7)
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LL_DMA_IsActiveFlag_HT7,
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#endif /* LL_DMA_ISR_HTIF7 */
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#if defined(LL_DMA_ISR_HTIF8)
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LL_DMA_IsActiveFlag_HT8,
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#endif /* LL_DMA_ISR_HTIF8 */
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};
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u32_t (*func_ll_is_active_tc[])(DMA_TypeDef *DMAx) = {
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LL_DMA_IsActiveFlag_TC1,
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LL_DMA_IsActiveFlag_TC2,
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LL_DMA_IsActiveFlag_TC3,
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LL_DMA_IsActiveFlag_TC4,
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LL_DMA_IsActiveFlag_TC5,
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#if defined(LL_DMA_ISR_TCIF6)
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LL_DMA_IsActiveFlag_TC6,
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#endif /* LL_DMA_ISR_TCIF6 */
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#if defined(LL_DMA_ISR_TCIF7)
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LL_DMA_IsActiveFlag_TC7,
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#endif /* LL_DMA_ISR_TCIF7 */
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#if defined(LL_DMA_ISR_TCIF8)
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LL_DMA_IsActiveFlag_TC8,
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#endif /* LL_DMA_ISR_TCIF8 */
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};
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static void (*func_ll_clear_te[])(DMA_TypeDef *DMAx) = {
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LL_DMA_ClearFlag_TE1,
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LL_DMA_ClearFlag_TE2,
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LL_DMA_ClearFlag_TE3,
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LL_DMA_ClearFlag_TE4,
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LL_DMA_ClearFlag_TE5,
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#if defined(LL_DMA_IFCR_CTEIF6)
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LL_DMA_ClearFlag_TE6,
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#endif /* LL_DMA_IFCR_CTEIF6 */
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#if defined(LL_DMA_IFCR_CTEIF7)
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LL_DMA_ClearFlag_TE7,
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#endif /* LL_DMA_IFCR_CTEIF7 */
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#if defined(LL_DMA_IFCR_CTEIF8)
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LL_DMA_ClearFlag_TE8,
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#endif /* LL_DMA_IFCR_CTEIF8 */
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};
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void (*func_ll_clear_gi[])(DMA_TypeDef *DMAx) = {
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LL_DMA_ClearFlag_GI1,
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LL_DMA_ClearFlag_GI2,
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LL_DMA_ClearFlag_GI3,
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LL_DMA_ClearFlag_GI4,
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LL_DMA_ClearFlag_GI5,
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#if defined(LL_DMA_IFCR_CGIF6)
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LL_DMA_ClearFlag_GI6,
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#endif /* LL_DMA_IFCR_CGIF6 */
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#if defined(LL_DMA_IFCR_CGIF7)
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LL_DMA_ClearFlag_GI7,
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#endif /* LL_DMA_IFCR_CGIF7 */
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#if defined(LL_DMA_IFCR_CGIF8)
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LL_DMA_ClearFlag_GI8,
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#endif /* LL_DMA_IFCR_CGIF8 */
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};
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static u32_t (*func_ll_is_active_te[])(DMA_TypeDef *DMAx) = {
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LL_DMA_IsActiveFlag_TE1,
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LL_DMA_IsActiveFlag_TE2,
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LL_DMA_IsActiveFlag_TE3,
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LL_DMA_IsActiveFlag_TE4,
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LL_DMA_IsActiveFlag_TE5,
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#if defined(LL_DMA_IFCR_CTEIF6)
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LL_DMA_IsActiveFlag_TE6,
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#endif /* LL_DMA_IFCR_CTEIF6 */
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#if defined(LL_DMA_IFCR_CTEIF7)
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LL_DMA_IsActiveFlag_TE7,
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#endif /* LL_DMA_IFCR_CTEIF7 */
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#if defined(LL_DMA_IFCR_CTEIF8)
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LL_DMA_IsActiveFlag_TE8,
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#endif /* LL_DMA_IFCR_CTEIF8 */
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};
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u32_t (*func_ll_is_active_gi[])(DMA_TypeDef *DMAx) = {
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LL_DMA_IsActiveFlag_GI1,
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LL_DMA_IsActiveFlag_GI2,
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LL_DMA_IsActiveFlag_GI3,
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LL_DMA_IsActiveFlag_GI4,
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LL_DMA_IsActiveFlag_GI5,
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#if defined(LL_DMA_IFCR_CGIF6)
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LL_DMA_IsActiveFlag_GI6,
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#endif /* LL_DMA_IFCR_CGIF6 */
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#if defined(LL_DMA_IFCR_CGIF7)
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LL_DMA_IsActiveFlag_GI7,
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#endif /* LL_DMA_IFCR_CGIF7 */
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#if defined(LL_DMA_IFCR_CGIF8)
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LL_DMA_IsActiveFlag_GI8,
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#endif /* LL_DMA_IFCR_CGIF8 */
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};
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void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, u32_t id)
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{
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LOG_INF("tc: %d, ht: %d, te: %d, gi: %d",
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func_ll_is_active_tc[id](dma),
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func_ll_is_active_ht[id](dma),
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func_ll_is_active_te[id](dma),
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func_ll_is_active_gi[id](dma));
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}
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void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, u32_t id)
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{
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func_ll_clear_te[id](dma);
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}
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bool stm32_dma_is_irq_happened(DMA_TypeDef *dma, u32_t id)
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{
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if (func_ll_is_active_te[id](dma)) {
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return true;
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}
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return false;
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}
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bool stm32_dma_is_unexpected_irq_happened(DMA_TypeDef *dma, u32_t id)
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{
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/* Preserve for future amending. */
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return false;
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}
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void stm32_dma_enable_stream(DMA_TypeDef *dma, u32_t id)
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{
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LL_DMA_EnableChannel(dma, table_ll_stream[id]);
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}
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int stm32_dma_disable_stream(DMA_TypeDef *dma, u32_t id)
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{
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if (!LL_DMA_IsEnabledChannel(dma, table_ll_stream[id])) {
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return 0;
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}
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LL_DMA_DisableChannel(dma, table_ll_stream[id]);
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return -EAGAIN;
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}
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