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https://github.com/zephyrproject-rtos/zephyr
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113b016b51
The stm32_dma_disable_stream first checked if the stream was disabled and if so returned OK. If it wasn't disabled it tried to disable it and returned -EAGAIN. The function is used in loops that try to disable the stream by calling this function and if it fails wait for 1ms and retry. Becuase this function the first time (if the stream wasn't disabled already) fails there is always a 1 ms delay. For the SPI driver, that has a RX and TX stream, this means a 2ms delay between the last data and CS going high. By first trying to disable the stream and than checking if it succeded most of the time the first call disables the stream and the 1ms delay isn't needed. Signed-off-by: Erwin Rol <erwin@erwinrol.com>
472 lines
10 KiB
C
472 lines
10 KiB
C
/*
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* Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief DMA low level driver implementation for F2/F4/F7 series SoCs.
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*/
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#include "dma_stm32.h"
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#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(dma_stm32_v1);
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/* DMA burst length */
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#define BURST_TRANS_LENGTH_1 0
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uint32_t dma_stm32_id_to_stream(uint32_t id)
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{
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static const uint32_t stream_nr[] = {
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LL_DMA_STREAM_0,
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LL_DMA_STREAM_1,
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LL_DMA_STREAM_2,
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LL_DMA_STREAM_3,
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LL_DMA_STREAM_4,
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LL_DMA_STREAM_5,
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LL_DMA_STREAM_6,
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LL_DMA_STREAM_7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr));
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return stream_nr[id];
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}
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uint32_t dma_stm32_slot_to_channel(uint32_t slot)
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{
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static const uint32_t channel_nr[] = {
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LL_DMA_CHANNEL_0,
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LL_DMA_CHANNEL_1,
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LL_DMA_CHANNEL_2,
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LL_DMA_CHANNEL_3,
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LL_DMA_CHANNEL_4,
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LL_DMA_CHANNEL_5,
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LL_DMA_CHANNEL_6,
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LL_DMA_CHANNEL_7,
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};
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__ASSERT_NO_MSG(slot < ARRAY_SIZE(channel_nr));
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return channel_nr[slot];
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}
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void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_HT0,
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LL_DMA_ClearFlag_HT1,
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LL_DMA_ClearFlag_HT2,
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LL_DMA_ClearFlag_HT3,
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LL_DMA_ClearFlag_HT4,
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LL_DMA_ClearFlag_HT5,
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LL_DMA_ClearFlag_HT6,
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LL_DMA_ClearFlag_HT7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_TC0,
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LL_DMA_ClearFlag_TC1,
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LL_DMA_ClearFlag_TC2,
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LL_DMA_ClearFlag_TC3,
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LL_DMA_ClearFlag_TC4,
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LL_DMA_ClearFlag_TC5,
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LL_DMA_ClearFlag_TC6,
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LL_DMA_ClearFlag_TC7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_HT0,
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LL_DMA_IsActiveFlag_HT1,
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LL_DMA_IsActiveFlag_HT2,
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LL_DMA_IsActiveFlag_HT3,
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LL_DMA_IsActiveFlag_HT4,
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LL_DMA_IsActiveFlag_HT5,
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LL_DMA_IsActiveFlag_HT6,
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LL_DMA_IsActiveFlag_HT7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_TC0,
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LL_DMA_IsActiveFlag_TC1,
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LL_DMA_IsActiveFlag_TC2,
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LL_DMA_IsActiveFlag_TC3,
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LL_DMA_IsActiveFlag_TC4,
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LL_DMA_IsActiveFlag_TC5,
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LL_DMA_IsActiveFlag_TC6,
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LL_DMA_IsActiveFlag_TC7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_TE0,
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LL_DMA_ClearFlag_TE1,
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LL_DMA_ClearFlag_TE2,
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LL_DMA_ClearFlag_TE3,
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LL_DMA_ClearFlag_TE4,
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LL_DMA_ClearFlag_TE5,
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LL_DMA_ClearFlag_TE6,
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LL_DMA_ClearFlag_TE7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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void dma_stm32_clear_dme(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_DME0,
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LL_DMA_ClearFlag_DME1,
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LL_DMA_ClearFlag_DME2,
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LL_DMA_ClearFlag_DME3,
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LL_DMA_ClearFlag_DME4,
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LL_DMA_ClearFlag_DME5,
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LL_DMA_ClearFlag_DME6,
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LL_DMA_ClearFlag_DME7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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void dma_stm32_clear_fe(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_clear_flag_func func[] = {
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LL_DMA_ClearFlag_FE0,
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LL_DMA_ClearFlag_FE1,
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LL_DMA_ClearFlag_FE2,
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LL_DMA_ClearFlag_FE3,
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LL_DMA_ClearFlag_FE4,
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LL_DMA_ClearFlag_FE5,
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LL_DMA_ClearFlag_FE6,
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LL_DMA_ClearFlag_FE7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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func[id](DMAx);
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}
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bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_TE0,
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LL_DMA_IsActiveFlag_TE1,
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LL_DMA_IsActiveFlag_TE2,
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LL_DMA_IsActiveFlag_TE3,
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LL_DMA_IsActiveFlag_TE4,
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LL_DMA_IsActiveFlag_TE5,
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LL_DMA_IsActiveFlag_TE6,
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LL_DMA_IsActiveFlag_TE7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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bool dma_stm32_is_dme_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_DME0,
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LL_DMA_IsActiveFlag_DME1,
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LL_DMA_IsActiveFlag_DME2,
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LL_DMA_IsActiveFlag_DME3,
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LL_DMA_IsActiveFlag_DME4,
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LL_DMA_IsActiveFlag_DME5,
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LL_DMA_IsActiveFlag_DME6,
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LL_DMA_IsActiveFlag_DME7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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bool dma_stm32_is_fe_active(DMA_TypeDef *DMAx, uint32_t id)
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{
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static const dma_stm32_check_flag_func func[] = {
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LL_DMA_IsActiveFlag_FE0,
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LL_DMA_IsActiveFlag_FE1,
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LL_DMA_IsActiveFlag_FE2,
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LL_DMA_IsActiveFlag_FE3,
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LL_DMA_IsActiveFlag_FE4,
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LL_DMA_IsActiveFlag_FE5,
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LL_DMA_IsActiveFlag_FE6,
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LL_DMA_IsActiveFlag_FE7,
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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return func[id](DMAx);
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}
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void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id)
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{
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LOG_INF("tc: %d, ht: %d, te: %d, dme: %d, fe: %d",
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dma_stm32_is_tc_active(dma, id),
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dma_stm32_is_ht_active(dma, id),
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dma_stm32_is_te_active(dma, id),
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dma_stm32_is_dme_active(dma, id),
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dma_stm32_is_fe_active(dma, id));
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}
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static inline bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return LL_DMA_IsEnabledIT_TC(dma, id) &&
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dma_stm32_is_tc_active(dma, id);
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}
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static inline bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return LL_DMA_IsEnabledIT_HT(dma, id) &&
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dma_stm32_is_ht_active(dma, id);
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}
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static inline bool stm32_dma_is_te_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return LL_DMA_IsEnabledIT_TE(dma, id) &&
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dma_stm32_is_te_active(dma, id);
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}
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static inline bool stm32_dma_is_dme_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return LL_DMA_IsEnabledIT_DME(dma, id) &&
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dma_stm32_is_dme_active(dma, id);
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}
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static inline bool stm32_dma_is_fe_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return LL_DMA_IsEnabledIT_FE(dma, id) &&
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dma_stm32_is_fe_active(dma, id);
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}
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bool stm32_dma_is_irq_active(DMA_TypeDef *dma, uint32_t id)
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{
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return stm32_dma_is_tc_irq_active(dma, id) ||
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stm32_dma_is_ht_irq_active(dma, id) ||
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stm32_dma_is_te_irq_active(dma, id) ||
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stm32_dma_is_dme_irq_active(dma, id) ||
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stm32_dma_is_fe_irq_active(dma, id);
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}
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void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, uint32_t id)
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{
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dma_stm32_clear_te(dma, id);
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dma_stm32_clear_dme(dma, id);
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dma_stm32_clear_fe(dma, id);
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}
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bool stm32_dma_is_irq_happened(DMA_TypeDef *dma, uint32_t id)
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{
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if (dma_stm32_is_fe_active(dma, id) && LL_DMA_IsEnabledIT_FE(dma, id)) {
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return true;
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}
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return false;
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}
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bool stm32_dma_is_unexpected_irq_happened(DMA_TypeDef *dma, uint32_t id)
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{
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if (dma_stm32_is_fe_active(dma, id) && LL_DMA_IsEnabledIT_FE(dma, id)) {
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LOG_ERR("FiFo error.");
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stm32_dma_dump_stream_irq(dma, id);
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stm32_dma_clear_stream_irq(dma, id);
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return true;
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}
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return false;
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}
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void stm32_dma_enable_stream(DMA_TypeDef *dma, uint32_t id)
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{
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LL_DMA_EnableStream(dma, dma_stm32_id_to_stream(id));
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}
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int stm32_dma_disable_stream(DMA_TypeDef *dma, uint32_t id)
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{
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LL_DMA_DisableStream(dma, dma_stm32_id_to_stream(id));
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if (!LL_DMA_IsEnabledStream(dma, dma_stm32_id_to_stream(id))) {
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return 0;
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}
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return -EAGAIN;
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}
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void stm32_dma_disable_fifo_irq(DMA_TypeDef *dma, uint32_t id)
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{
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LL_DMA_DisableIT_FE(dma, dma_stm32_id_to_stream(id));
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}
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void stm32_dma_config_channel_function(DMA_TypeDef *dma, uint32_t id, uint32_t slot)
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{
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LL_DMA_SetChannelSelection(dma, dma_stm32_id_to_stream(id),
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dma_stm32_slot_to_channel(slot));
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}
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uint32_t stm32_dma_get_mburst(struct dma_config *config, bool source_periph)
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{
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uint32_t memory_burst;
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if (source_periph) {
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memory_burst = config->dest_burst_length;
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} else {
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memory_burst = config->source_burst_length;
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}
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switch (memory_burst) {
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case 1:
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return LL_DMA_MBURST_SINGLE;
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case 4:
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return LL_DMA_MBURST_INC4;
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case 8:
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return LL_DMA_MBURST_INC8;
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case 16:
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return LL_DMA_MBURST_INC16;
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default:
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LOG_ERR("Memory burst size error,"
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"using single burst as default");
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return LL_DMA_MBURST_SINGLE;
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}
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}
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uint32_t stm32_dma_get_pburst(struct dma_config *config, bool source_periph)
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{
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uint32_t periph_burst;
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if (source_periph) {
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periph_burst = config->source_burst_length;
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} else {
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periph_burst = config->dest_burst_length;
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}
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switch (periph_burst) {
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case 1:
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return LL_DMA_PBURST_SINGLE;
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case 4:
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return LL_DMA_PBURST_INC4;
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case 8:
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return LL_DMA_PBURST_INC8;
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case 16:
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return LL_DMA_PBURST_INC16;
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default:
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LOG_ERR("Peripheral burst size error,"
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"using single burst as default");
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return LL_DMA_PBURST_SINGLE;
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}
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}
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/*
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* This function checks if the msize, mburst and fifo level is
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* compitable. If they are not compitable, refer to the 'FIFO'
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* section in the 'DMA' chapter in the Reference Manual for more
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* information.
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* break is emitted since every path of the code has 'return'.
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* This function does not have the obligation of checking the parameters.
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*/
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bool stm32_dma_check_fifo_mburst(LL_DMA_InitTypeDef *DMAx)
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{
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uint32_t msize = DMAx->MemoryOrM2MDstDataSize;
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uint32_t fifo_level = DMAx->FIFOThreshold;
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uint32_t mburst = DMAx->MemBurst;
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switch (msize) {
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case LL_DMA_MDATAALIGN_BYTE:
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switch (mburst) {
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case LL_DMA_MBURST_INC4:
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return true;
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case LL_DMA_MBURST_INC8:
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if (fifo_level == LL_DMA_FIFOTHRESHOLD_1_2 ||
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fifo_level == LL_DMA_FIFOTHRESHOLD_FULL) {
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return true;
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} else {
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return false;
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}
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case LL_DMA_MBURST_INC16:
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if (fifo_level == LL_DMA_FIFOTHRESHOLD_FULL) {
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return true;
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} else {
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return false;
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}
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}
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case LL_DMA_MDATAALIGN_HALFWORD:
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switch (mburst) {
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case LL_DMA_MBURST_INC4:
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if (fifo_level == LL_DMA_FIFOTHRESHOLD_1_2 ||
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fifo_level == LL_DMA_FIFOTHRESHOLD_FULL) {
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return true;
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} else {
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return false;
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}
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case LL_DMA_MBURST_INC8:
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if (fifo_level == LL_DMA_FIFOTHRESHOLD_FULL) {
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return true;
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} else {
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return false;
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}
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case LL_DMA_MBURST_INC16:
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return false;
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}
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case LL_DMA_MDATAALIGN_WORD:
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if (mburst == LL_DMA_MBURST_INC4 &&
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fifo_level == LL_DMA_FIFOTHRESHOLD_FULL) {
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return true;
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} else {
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return false;
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}
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default:
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return false;
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}
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}
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uint32_t stm32_dma_get_fifo_threshold(uint16_t fifo_mode_control)
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{
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switch (fifo_mode_control) {
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case 0:
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return LL_DMA_FIFOTHRESHOLD_1_4;
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case 1:
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return LL_DMA_FIFOTHRESHOLD_1_2;
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case 2:
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return LL_DMA_FIFOTHRESHOLD_3_4;
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case 3:
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return LL_DMA_FIFOTHRESHOLD_FULL;
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default:
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LOG_WRN("FIFO threshold parameter error, reset to 1/4");
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return LL_DMA_FIFOTHRESHOLD_1_4;
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}
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}
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