Alexandre Bourdiol 4cf1d4380e arch: arm: aarch32:cortex_m: timing.c: cortex M7 may need DWT unlock ... On Cortex M7, we need to check the optional presence of Lock Access Register (LAR) which is indicated in Lock Status Register (LSR). When present, a special access token must be written to unlock DWT registers. Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>		2020-12-02 10:58:08 +02:00
..
arc	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
arm	arch: arm: aarch32:cortex_m: timing.c: cortex M7 may need DWT unlock	2020-12-02 10:58:08 +02:00
common
nios2	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
posix
riscv	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
sparc	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
x86	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
xtensa	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
CMakeLists.txt
Kconfig	arch: mem protect Kconfig cleanups	2020-11-18 08:02:08 -05:00