mirror of
https://github.com/zephyrproject-rtos/zephyr
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43bea395d3
Commit c0bd8a0ce4 ("api: dma: dma api update") introduced some new APIs
and deprecated the old ones. Let's move to the new API before the old
calls are completely removed.
Change-Id: I21795fa20124f8101c56b0fceb0f0d9afd96b0f0
Signed-off-by: Lee Jones <lee.jones@linaro.org>
493 lines
16 KiB
C
493 lines
16 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_DMA_LEVEL
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#include <board.h>
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#include <device.h>
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#include <dma.h>
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#include <errno.h>
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#include <init.h>
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#include <logging/sys_log.h>
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#include <stdio.h>
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#include <string.h>
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#include <clock_control/stm32_clock_control.h>
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#define DMA_STM32_MAX_CHANNELS 8 /* Number of channels per controller */
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#define DMA_STM32_MAX_DEVS 2 /* Number of controllers */
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#define DMA_STM32_1 0 /* First DMA controller */
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#define DMA_STM32_2 1 /* Second DMA controller */
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#define DMA_STM32_IRQ_PRI CONFIG_DMA_0_IRQ_PRI
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struct dma_stm32_chan_reg {
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/* Shared registers */
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uint32_t lisr;
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uint32_t hisr;
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uint32_t lifcr;
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uint32_t hifcr;
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/* Per channel registers */
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uint32_t scr;
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uint32_t sndtr;
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uint32_t spar;
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uint32_t sm0ar;
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uint32_t sm1ar;
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uint32_t sfcr;
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};
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struct dma_stm32_chan {
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uint32_t id;
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uint32_t direction;
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struct device *dev;
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struct dma_stm32_chan_reg regs;
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bool busy;
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void (*dma_callback)(struct device *dev, uint32_t channel,
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int error_code);
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};
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static struct dma_stm32_device {
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uint32_t base;
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struct device *clk;
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struct dma_stm32_chan chan[DMA_STM32_MAX_CHANNELS];
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bool mem2mem;
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} ddata[DMA_STM32_MAX_DEVS];
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struct dma_stm32_config {
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struct stm32f4x_pclken pclken;
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void (*config)(struct dma_stm32_device *);
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};
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/* DMA direction */
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#define DMA_STM32_DEV_TO_MEM 0
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#define DMA_STM32_MEM_TO_DEV 1
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#define DMA_STM32_MEM_TO_MEM 2
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/* DMA priority level */
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#define DMA_STM32_PRIORITY_LOW 0
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#define DMA_STM32_PRIORITY_MEDIUM 1
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#define DMA_STM32_PRIORITY_HIGH 2
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#define DMA_STM32_PRIORITY_VERY_HIGH 3
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/* DMA FIFO threshold selection */
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#define DMA_STM32_FIFO_THRESHOLD_1QUARTERFULL 0
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#define DMA_STM32_FIFO_THRESHOLD_HALFFULL 1
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#define DMA_STM32_FIFO_THRESHOLD_3QUARTERSFULL 2
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#define DMA_STM32_FIFO_THRESHOLD_FULL 3
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/* Maximum data sent in single transfer (Bytes) */
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#define DMA_STM32_MAX_DATA_ITEMS 0xffff
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#define BITS_PER_LONG 32
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#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
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#define DMA_STM32_1_BASE 0x40026000
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#define DMA_STM32_2_BASE 0x40026400
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/* Shared registers */
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#define DMA_STM32_LISR 0x00 /* DMA low int status reg */
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#define DMA_STM32_HISR 0x04 /* DMA high int status reg */
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#define DMA_STM32_LIFCR 0x08 /* DMA low int flag clear reg */
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#define DMA_STM32_HIFCR 0x0c /* DMA high int flag clear reg */
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#define DMA_STM32_FEI BIT(0) /* FIFO error interrupt */
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#define RESERVED_1 BIT(1)
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#define DMA_STM32_DMEI BIT(2) /* Direct mode error interrupt */
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#define DMA_STM32_TEI BIT(3) /* Transfer error interrupt */
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#define DMA_STM32_HTI BIT(4) /* Transfer half complete interrupt */
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#define DMA_STM32_TCI BIT(5) /* Transfer complete interrupt */
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/* DMA Stream x Configuration Register */
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#define DMA_STM32_SCR(x) (0x10 + 0x18 * (x))
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#define DMA_STM32_SCR_EN BIT(0) /* Stream Enable */
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#define DMA_STM32_SCR_DMEIE BIT(1) /* Direct Mode Err Int En */
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#define DMA_STM32_SCR_TEIE BIT(2) /* Transfer Error Int En */
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#define DMA_STM32_SCR_HTIE BIT(3) /* Transfer 1/2 Comp Int En */
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#define DMA_STM32_SCR_TCIE BIT(4) /* Transfer Comp Int En */
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#define DMA_STM32_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */
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#define DMA_STM32_SCR_DIR_MASK GENMASK(7, 6) /* Transfer direction */
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#define DMA_STM32_SCR_CIRC BIT(8) /* Circular mode */
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#define DMA_STM32_SCR_PINC BIT(9) /* Peripheral increment mode */
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#define DMA_STM32_SCR_MINC BIT(10) /* Memory increment mode */
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#define DMA_STM32_SCR_PSIZE_MASK GENMASK(12, 11) /* Periph data size */
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#define DMA_STM32_SCR_MSIZE_MASK GENMASK(14, 13) /* Memory data size */
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#define DMA_STM32_SCR_PINCOS BIT(15) /* Periph inc offset size */
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#define DMA_STM32_SCR_PL_MASK GENMASK(17, 16) /* Priority level */
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#define DMA_STM32_SCR_DBM BIT(18) /* Double Buffer Mode */
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#define DMA_STM32_SCR_CT BIT(19) /* Target in double buffer */
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#define DMA_STM32_SCR_PBURST_MASK GENMASK(22, 21) /* Periph burst size */
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#define DMA_STM32_SCR_MBURST_MASK GENMASK(24, 23) /* Memory burst size */
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/* Setting MACROS */
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#define DMA_STM32_SCR_DIR(n) ((n & 0x3) << 6)
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#define DMA_STM32_SCR_PSIZE(n) ((n & 0x3) << 11)
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#define DMA_STM32_SCR_MSIZE(n) ((n & 0x3) << 13)
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#define DMA_STM32_SCR_PL(n) ((n & 0x3) << 16)
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#define DMA_STM32_SCR_PBURST(n) ((n & 0x3) << 21)
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#define DMA_STM32_SCR_MBURST(n) ((n & 0x3) << 23)
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#define DMA_STM32_SCR_REQ(n) ((n & 0x7) << 25)
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/* Getting MACROS */
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#define DMA_STM32_SCR_PSIZE_GET(n) ((n & DMA_STM32_SCR_PSIZE_MASK) >> 11)
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#define DMA_STM32_SCR_CFG_MASK (DMA_STM32_SCR_PINC \
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| DMA_STM32_SCR_MINC \
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| DMA_STM32_SCR_PINCOS \
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| DMA_STM32_SCR_PL_MASK)
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#define DMA_STM32_SCR_IRQ_MASK (DMA_STM32_SCR_TCIE \
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| DMA_STM32_SCR_TEIE \
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| DMA_STM32_SCR_DMEIE)
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/* DMA stream x number of data register (len) */
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#define DMA_STM32_SNDTR(x) (0x14 + 0x18 * (x))
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/* DMA stream peripheral address register (source) */
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#define DMA_STM32_SPAR(x) (0x18 + 0x18 * (x))
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/* DMA stream x memory 0 address register (destination) */
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#define DMA_STM32_SM0AR(x) (0x1c + 0x18 * (x))
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/* DMA stream x memory 1 address register (destination - double buffer) */
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#define DMA_STM32_SM1AR(x) (0x20 + 0x18 * (x))
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/* DMA stream x FIFO control register */
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#define DMA_STM32_SFCR(x) (0x24 + 0x18 * (x))
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#define DMA_STM32_SFCR_FTH_MASK GENMASK(1, 0) /* FIFO threshold */
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#define DMA_STM32_SFCR_DMDIS BIT(2) /* Direct mode disable */
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#define DMA_STM32_SFCR_STAT_MASK GENMASK(5, 3) /* FIFO status */
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#define RESERVED_6 BIT(6) /* Reserved */
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#define DMA_STM32_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */
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/* Setting MACROS */
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#define DMA_STM32_SFCR_FTH(n) (n & DMA_STM32_SFCR_FTH_MASK)
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#define DMA_STM32_SFCR_MASK (DMA_STM32_SFCR_FEIE \
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| DMA_STM32_SFCR_DMDIS)
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#define SYS_LOG_U32 __attribute((__unused__)) uint32_t
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static void dma_stm32_1_config(struct dma_stm32_device *ddata);
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static void dma_stm32_2_config(struct dma_stm32_device *ddata);
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static uint32_t dma_stm32_read(struct dma_stm32_device *ddata, uint32_t reg)
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{
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return sys_read32(ddata->base + reg);
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}
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static void dma_stm32_write(struct dma_stm32_device *ddata,
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uint32_t reg, uint32_t val)
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{
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sys_write32(val, ddata->base + reg);
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}
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static uint32_t dma_stm32_irq_status(struct dma_stm32_device *ddata,
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uint32_t channel)
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{
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uint32_t irqs;
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if (channel & 4) {
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irqs = dma_stm32_read(ddata, DMA_STM32_HISR);
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} else {
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irqs = dma_stm32_read(ddata, DMA_STM32_LISR);
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}
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return (irqs >> (((channel & 2) << 3) | ((channel & 1) * 6)));
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}
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static void dma_stm32_irq_clear(struct dma_stm32_device *ddata,
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uint32_t channel, uint32_t irqs)
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{
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irqs = irqs << (((channel & 2) << 3) | ((channel & 1) * 6));
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if (channel & 4) {
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dma_stm32_write(ddata, DMA_STM32_HIFCR, irqs);
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} else {
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dma_stm32_write(ddata, DMA_STM32_LIFCR, irqs);
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}
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}
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static void dma_stm32_irq_handler(void *arg, uint32_t channel)
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{
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struct device *dev = arg;
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan *chan = &ddata->chan[channel];
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uint32_t irqstatus, config, sfcr;
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irqstatus = dma_stm32_irq_status(ddata, channel);
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config = dma_stm32_read(ddata, DMA_STM32_SCR(channel));
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sfcr = dma_stm32_read(ddata, DMA_STM32_SFCR(channel));
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/* Silently ignore spurious transfer half complete IRQ */
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if (irqstatus & DMA_STM32_HTI) {
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dma_stm32_irq_clear(ddata, channel, DMA_STM32_HTI);
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return;
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}
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chan->busy = false;
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if ((irqstatus & DMA_STM32_TCI) && (config & DMA_STM32_SCR_TCIE)) {
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dma_stm32_irq_clear(ddata, channel, DMA_STM32_TCI);
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chan->dma_callback(chan->dev, channel, 0);
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} else {
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SYS_LOG_ERR("Internal error: IRQ status: 0x%x\n", irqstatus);
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dma_stm32_irq_clear(ddata, channel, irqstatus);
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chan->dma_callback(chan->dev, channel, -EIO);
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}
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}
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static int dma_stm32_disable_chan(struct dma_stm32_device *ddata,
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uint32_t channel)
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{
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uint32_t config;
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int count = 0;
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int ret = 0;
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for (;;) {
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config = dma_stm32_read(ddata, DMA_STM32_SCR(channel));
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/* Channel already disabled */
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if (!(config & DMA_STM32_SCR_EN)) {
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return 0;
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}
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/* Try to disable channel */
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dma_stm32_write(ddata, DMA_STM32_SCR(channel),
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config &= ~DMA_STM32_SCR_EN);
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/* After trying for 5 seconds, give up */
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k_sleep(K_SECONDS(5));
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if (count++ > (5 * 1000) / 50) {
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SYS_LOG_ERR("DMA error: Channel in use\n");
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return -EBUSY;
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}
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}
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return ret;
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}
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static int dma_stm32_config_memcpy(struct device *dev, uint32_t channel)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan_reg *regs = &ddata->chan[channel].regs;
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if (!ddata->mem2mem) {
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SYS_LOG_ERR("%s does not support mem-to-mem transfers\n",
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dev->config->name);
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return -EINVAL;
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}
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regs->scr = DMA_STM32_SCR_DIR(DMA_STM32_MEM_TO_MEM) |
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DMA_STM32_SCR_MINC | /* Memory increment mode */
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DMA_STM32_SCR_PINC | /* Peripheral increment mode */
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DMA_STM32_SCR_TCIE | /* Transfer comp IRQ enable */
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DMA_STM32_SCR_TEIE; /* Transfer error IRQ enable */
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regs->sfcr = DMA_STM32_SFCR_DMDIS | /* Direct mode disable */
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DMA_STM32_SFCR_FTH(DMA_STM32_FIFO_THRESHOLD_FULL) |
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DMA_STM32_SFCR_FEIE; /* FIFI error IRQ enable */
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return 0;
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}
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static int dma_stm32_config(struct device *dev, uint32_t channel,
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struct dma_config *config)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan *chan = &ddata->chan[channel];
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struct dma_stm32_chan_reg *regs = &ddata->chan[channel].regs;
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if (config->channel_direction != MEMORY_TO_MEMORY) {
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SYS_LOG_ERR("Only mem-to-mem transfers currently supported\n");
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return -ENOTSUP;
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}
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if (chan->busy) {
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return -EBUSY;
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}
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chan->busy = true;
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chan->dma_callback = config->dma_callback;
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regs->spar = (uint32_t)config->head_block->source_address;
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regs->sm0ar = (uint32_t)config->head_block->dest_address;
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regs->sndtr = config->head_block->block_size;
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return dma_stm32_config_memcpy(dev, channel);
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}
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static int dma_stm32_start(struct device *dev, uint32_t channel)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan_reg *regs = &ddata->chan[channel].regs;
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uint32_t irqstatus;
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int ret;
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ret = dma_stm32_disable_chan(ddata, channel);
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if (ret) {
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return ret;
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}
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dma_stm32_write(ddata, DMA_STM32_SCR(channel), regs->scr);
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dma_stm32_write(ddata, DMA_STM32_SPAR(channel), regs->spar);
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dma_stm32_write(ddata, DMA_STM32_SM0AR(channel), regs->sm0ar);
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dma_stm32_write(ddata, DMA_STM32_SFCR(channel), regs->sfcr);
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dma_stm32_write(ddata, DMA_STM32_SM1AR(channel), regs->sm1ar);
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dma_stm32_write(ddata, DMA_STM32_SNDTR(channel), regs->sndtr);
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/* Clear remanent IRQs from previous transfers */
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irqstatus = dma_stm32_irq_status(ddata, channel);
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if (irqstatus) {
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dma_stm32_irq_clear(ddata, channel, irqstatus);
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}
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/* Push the start button */
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dma_stm32_write(ddata, DMA_STM32_SCR(channel),
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regs->scr | DMA_STM32_SCR_EN);
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return 0;
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}
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static int dma_stm32_stop(struct device *dev, uint32_t channel)
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{
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return 0;
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}
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static int dma_stm32_init(struct device *dev)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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const struct dma_stm32_config *cdata = dev->config->config_info;
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int i;
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for (i = 0; i < DMA_STM32_MAX_CHANNELS; i++) {
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ddata->chan[i].id = i;
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ddata->chan[i].dev = dev;
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ddata->chan[i].busy = false;
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}
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/* Enable DMA clock */
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ddata->clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(ddata->clk);
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clock_control_on(ddata->clk, (clock_control_subsys_t *) &cdata->pclken);
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/* Set controller specific configuration */
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cdata->config(ddata);
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return 0;
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}
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static const struct dma_driver_api dma_funcs = {
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.config = dma_stm32_config,
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.start = dma_stm32_start,
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.stop = dma_stm32_stop,
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};
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const struct dma_stm32_config dma_stm32_1_cdata = {
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.pclken = { .bus = STM32F4X_CLOCK_BUS_AHB1,
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.enr = STM32F4X_CLOCK_ENABLE_DMA1 },
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.config = dma_stm32_1_config,
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};
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DEVICE_AND_API_INIT(dma_stm32_1, CONFIG_DMA_1_NAME, &dma_stm32_init,
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&ddata[DMA_STM32_1], &dma_stm32_1_cdata,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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(void *)&dma_funcs);
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static const struct dma_stm32_config dma_stm32_2_cdata = {
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.pclken = { .bus = STM32F4X_CLOCK_BUS_AHB1,
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.enr = STM32F4X_CLOCK_ENABLE_DMA2 },
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.config = dma_stm32_2_config,
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};
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DEVICE_AND_API_INIT(dma_stm32_2, CONFIG_DMA_2_NAME, &dma_stm32_init,
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&ddata[DMA_STM32_2], &dma_stm32_2_cdata,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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(void *)&dma_funcs);
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static void dma_stm32_irq_0(void *arg) { dma_stm32_irq_handler(arg, 0); }
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static void dma_stm32_irq_1(void *arg) { dma_stm32_irq_handler(arg, 1); }
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static void dma_stm32_irq_2(void *arg) { dma_stm32_irq_handler(arg, 2); }
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static void dma_stm32_irq_3(void *arg) { dma_stm32_irq_handler(arg, 3); }
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static void dma_stm32_irq_4(void *arg) { dma_stm32_irq_handler(arg, 4); }
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static void dma_stm32_irq_5(void *arg) { dma_stm32_irq_handler(arg, 5); }
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static void dma_stm32_irq_6(void *arg) { dma_stm32_irq_handler(arg, 6); }
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static void dma_stm32_irq_7(void *arg) { dma_stm32_irq_handler(arg, 7); }
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static void dma_stm32_1_config(struct dma_stm32_device *ddata)
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{
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ddata->base = DMA_STM32_1_BASE;
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IRQ_CONNECT(STM32F4_IRQ_DMA1_STREAM0, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_0, DEVICE_GET(dma_stm32_1), 0);
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irq_enable(STM32F4_IRQ_DMA1_STREAM0);
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IRQ_CONNECT(STM32F4_IRQ_DMA1_STREAM1, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_1, DEVICE_GET(dma_stm32_1), 0);
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irq_enable(STM32F4_IRQ_DMA1_STREAM1);
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IRQ_CONNECT(STM32F4_IRQ_DMA1_STREAM2, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_2, DEVICE_GET(dma_stm32_1), 0);
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irq_enable(STM32F4_IRQ_DMA1_STREAM2);
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IRQ_CONNECT(STM32F4_IRQ_DMA1_STREAM3, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_3, DEVICE_GET(dma_stm32_1), 0);
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irq_enable(STM32F4_IRQ_DMA1_STREAM3);
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IRQ_CONNECT(STM32F4_IRQ_DMA1_STREAM4, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_4, DEVICE_GET(dma_stm32_1), 0);
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irq_enable(STM32F4_IRQ_DMA1_STREAM4);
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IRQ_CONNECT(STM32F4_IRQ_DMA1_STREAM5, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_5, DEVICE_GET(dma_stm32_1), 0);
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irq_enable(STM32F4_IRQ_DMA1_STREAM5);
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IRQ_CONNECT(STM32F4_IRQ_DMA1_STREAM6, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_6, DEVICE_GET(dma_stm32_1), 0);
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irq_enable(STM32F4_IRQ_DMA1_STREAM6);
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IRQ_CONNECT(STM32F4_IRQ_DMA1_STREAM7, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_7, DEVICE_GET(dma_stm32_1), 0);
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irq_enable(STM32F4_IRQ_DMA1_STREAM7);
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}
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static void dma_stm32_2_config(struct dma_stm32_device *ddata)
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{
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ddata->base = DMA_STM32_2_BASE;
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ddata->mem2mem = true;
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IRQ_CONNECT(STM32F4_IRQ_DMA2_STREAM0, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_0, DEVICE_GET(dma_stm32_2), 0);
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irq_enable(STM32F4_IRQ_DMA2_STREAM0);
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IRQ_CONNECT(STM32F4_IRQ_DMA2_STREAM1, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_1, DEVICE_GET(dma_stm32_2), 0);
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irq_enable(STM32F4_IRQ_DMA2_STREAM1);
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IRQ_CONNECT(STM32F4_IRQ_DMA2_STREAM2, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_2, DEVICE_GET(dma_stm32_2), 0);
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irq_enable(STM32F4_IRQ_DMA2_STREAM2);
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IRQ_CONNECT(STM32F4_IRQ_DMA2_STREAM3, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_3, DEVICE_GET(dma_stm32_2), 0);
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irq_enable(STM32F4_IRQ_DMA2_STREAM3);
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IRQ_CONNECT(STM32F4_IRQ_DMA2_STREAM4, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_4, DEVICE_GET(dma_stm32_2), 0);
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irq_enable(STM32F4_IRQ_DMA2_STREAM4);
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IRQ_CONNECT(STM32F4_IRQ_DMA2_STREAM5, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_5, DEVICE_GET(dma_stm32_2), 0);
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irq_enable(STM32F4_IRQ_DMA2_STREAM5);
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IRQ_CONNECT(STM32F4_IRQ_DMA2_STREAM6, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_6, DEVICE_GET(dma_stm32_2), 0);
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irq_enable(STM32F4_IRQ_DMA2_STREAM6);
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IRQ_CONNECT(STM32F4_IRQ_DMA2_STREAM7, DMA_STM32_IRQ_PRI,
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dma_stm32_irq_7, DEVICE_GET(dma_stm32_2), 0);
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irq_enable(STM32F4_IRQ_DMA2_STREAM7);
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}
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