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43e23cf9f2
The Ambiq MSPI controller is implemented using the MSPI bus API. The hardware supports up to 48MHz octal SDR with XIP, scrambling and hardware command queue features. Signed-off-by: Swift Tian <swift.tian@ambiq.com>
8 lines
262 B
CMake
8 lines
262 B
CMake
# SPDX-License-Identifier: Apache-2.0
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zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/mspi.h)
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_MSPI_AMBIQ_AP3 mspi_ambiq_ap3.c)
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zephyr_library_sources_ifdef(CONFIG_MSPI_EMUL mspi_emul.c)
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