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https://github.com/zephyrproject-rtos/zephyr
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f540cbc5c5
Add Low Power States support to the power shim layer and show the usage in the quark_se sample. States are defined as follow: - SYS_POWER_STATE_CPU_LPS: SS2 with LPSS enabled - SYS_POWER_STATE_CPU_LPS_1: SS2 with LPSS disabled - SYS_POWER_STATE_CPU_LPS_2: SS1 with LPSS disabled Jira: ZEP-994 Change-Id: Ie4b93f6e539cb53fc035be00280b66b2cb0d9fea Signed-off-by: Julien Delayen <julien.delayen@intel.com>
63 lines
2.0 KiB
C
63 lines
2.0 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief ARCv2 Interrupt Unit device driver
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*
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* The ARCv2 interrupt unit has 16 allocated exceptions associated with
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* vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
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* The interrupt unit is optional in the ARCv2-based processors. When
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* building a processor, you can configure the processor to include an
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* interrupt unit. The ARCv2 interrupt unit is highly programmable.
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <board.h>
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extern void *_VectorTable;
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void _arc_v2_irq_unit_init(void)
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{
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int irq; /* the interrupt index */
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for (irq = 16; irq < CONFIG_NUM_IRQS; irq++) {
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY,
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(CONFIG_NUM_IRQ_PRIO_LEVELS-1)); /* lowest priority */
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_ENABLE, _ARC_V2_INT_DISABLE);
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER, _ARC_V2_INT_LEVEL);
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}
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}
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void _arc_v2_irq_unit_int_eoi(int irq)
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{
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_PULSE_CANCEL, 1);
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}
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void _arc_v2_irq_unit_trigger_set(int irq, unsigned int trigger)
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{
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER, trigger);
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}
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unsigned int _arc_v2_irq_unit_trigger_get(int irq)
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{
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
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return _arc_v2_aux_reg_read(_ARC_V2_IRQ_TRIGGER);
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}
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