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https://github.com/zephyrproject-rtos/zephyr
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0ba204083d
This adds SMP support for Intel S1000 SoC. Some of the start-up code is borrowed from ESP32. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
49 lines
709 B
Plaintext
49 lines
709 B
Plaintext
# XTENSA board configuration
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_INTEL_S1000
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config SOC
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default "intel_s1000"
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config IRQ_OFFLOAD_INTNUM
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default 0
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# S1000 does not have MISC0.
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# Since EXCSAVE7 is unused by Zephyr, use it instead.
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config XTENSA_KERNEL_CPU_PTR_SR
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default "EXCSAVE7"
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config SPI_DW_FIFO_DEPTH
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default 32
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 400000000 if XTENSA_TIMER
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default 38400000 if CAVS_TIMER
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if SMP
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config MP_NUM_CPUS
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default 2
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config XTENSA_TIMER
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default n
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config CAVS_TIMER
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default y
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config IPM
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default y
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config IPM_CAVS_IDC
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default y if IPM
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config SCHED_IPI_SUPPORTED
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default y if IPM_CAVS_IDC
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endif
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endif
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