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zephyr/soc/xtensa
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Daniel Leung 4962bf3875 soc: intel_s1000: fix SMP build error 
During devicetree macro changes, LPSRAM_BOOT_VECTOR_ADDR
pointed to another macro which was renamed to a non-existent
one. Fix it so that SMP builds again.

Fixes #24720

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-04-29 14:59:33 -05:00
..
esp32 arch: xtensa: replace DT_CPU_CLOCK_FREQUENCY with new dt macros 2020-04-22 11:38:33 -05:00
intel_apl_adsp soc: xtensa: rework DT_L2_SRAM and DT_L2_SRAM 2020-04-25 09:32:00 -05:00
intel_s1000 soc: intel_s1000: fix SMP build error 2020-04-29 14:59:33 -05:00
sample_controller arch: xtensa: replace DT_CPU_CLOCK_FREQUENCY with new dt macros 2020-04-22 11:38:33 -05:00