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In order ease readability of Kconfig.stm32 file, split series specific PLL configuration options into series specifc Kconfig files. This being done, we have now a similar pattern for series specific code and series specific Kconfig files. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
53 lines
1.6 KiB
Plaintext
53 lines
1.6 KiB
Plaintext
# Kconfig - STM32F2, STM32F4 and STM32F7 PLL configuration options
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#
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# Copyright (c) 2019 Linaro
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_STM32F2X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
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config CLOCK_STM32_PLL_M_DIVISOR
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int "Division factor for PLL VCO input clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 8
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range 2 63
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help
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PLLM division factor needs to be set correctly to ensure that the VCO
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input frequency ranges from 1 to 2 MHz. It is recommended to select a
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frequency of 2 MHz to limit PLL jitter.
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Allowed values: 2-63
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "Multiplier factor for PLL VCO output clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 336
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range 192 432 if SOC_STM32F401XE || SOC_SERIES_STM32F2X
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range 50 432
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help
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PLLN multiplier factor needs to be set correctly to ensure that the
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VCO output frequency is between 100 and 432 MHz, except on STM32F401
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where the frequency must be between 192 and 432 MHz.
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Allowed values: 50-432 (STM32F401: 192-432)
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL division factor for main system clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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range 2 8
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help
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PLLP division factor needs to be set correctly to not exceed 84MHz.
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Allowed values: 2, 4, 6, 8
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "Division factor for OTG FS, SDIO and RNG clocks"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 7
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range 2 15
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help
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The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
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need a frequency lower than or equal to 48 MHz to work correctly.
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Allowed values: 2-15
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endif # SOC_SERIES_STM32F2X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
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