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Enable cache operations before starting a DMA operation if the CPU has a cache. All the support was already in place, it just needs to be enabled. With the previous commits, it allows the I2S tests to pass on a SAM E70 Xplained board with the CPU cache enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> |
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.. | ||
CMakeLists.txt | ||
i2s_cavs.c | ||
i2s_cavs.h | ||
i2s_common.c | ||
i2s_handlers.c | ||
i2s_ll_stm32.c | ||
i2s_ll_stm32.h | ||
i2s_sam_ssc.c | ||
Kconfig | ||
Kconfig.cavs | ||
Kconfig.sam_ssc | ||
Kconfig.stm32 |