mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-28 09:15:21 +00:00
f49150cab6
Upcoming Nordic ICs that share many of the peripherals and architecture with the currently supported nRF5x ones are no longer part of the nRF5 family. In order to accomodate that, rename the SoC family from nrf5 to nrf, so that it can contain all of the members of the wider Nordic family. Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
70 lines
1.5 KiB
Plaintext
70 lines
1.5 KiB
Plaintext
# Kconfig.nrf5 - NRF5 UART configuration
|
|
#
|
|
# Copyright (c) 2016 Nordic Semiconductor ASA
|
|
#
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
#
|
|
|
|
menuconfig UART_NRF5
|
|
bool "Nordic Semiconductor NRF5 family processor UART driver"
|
|
default n
|
|
select SERIAL_HAS_DRIVER
|
|
select SERIAL_SUPPORT_INTERRUPT
|
|
depends on SOC_FAMILY_NRF
|
|
select GPIO_NRF5
|
|
help
|
|
This option enables the UART driver for Nordic Semiconductor nRF5
|
|
family processors. Note that there is only one
|
|
UART controller on nRF5 ICs.
|
|
|
|
config UART_NRF5_CLK_FREQ
|
|
int
|
|
default 16000000
|
|
depends on UART_NRF5
|
|
|
|
config UART_NRF5_FLOW_CONTROL
|
|
bool "Enable Flow Control"
|
|
default n
|
|
depends on UART_NRF5
|
|
help
|
|
Enable Flow Control. If selected, additionally two pins, RTS and CTS
|
|
has to be configured.
|
|
|
|
config UART_NRF5_GPIO_TX_PIN
|
|
int "TX Pin Number"
|
|
range 0 47 if SOC_NRF52840_QIAA
|
|
range 0 31
|
|
depends on UART_NRF5
|
|
depends on GPIO_NRF5
|
|
help
|
|
The GPIO pin to use for TX.
|
|
|
|
config UART_NRF5_GPIO_RX_PIN
|
|
int "RX Pin Number"
|
|
range 0 47 if SOC_NRF52840_QIAA
|
|
range 0 31
|
|
depends on UART_NRF5
|
|
depends on GPIO_NRF5
|
|
help
|
|
The GPIO pin to use for RX.
|
|
|
|
config UART_NRF5_GPIO_RTS_PIN
|
|
int "RTS Pin Number"
|
|
range 0 47 if SOC_NRF52840_QIAA
|
|
range 0 31
|
|
depends on UART_NRF5
|
|
depends on GPIO_NRF5
|
|
depends on UART_NRF5_FLOW_CONTROL
|
|
help
|
|
The GPIO pin to use for RTS.
|
|
|
|
config UART_NRF5_GPIO_CTS_PIN
|
|
int "CTS Pin Number"
|
|
range 0 47 if SOC_NRF52840_QIAA
|
|
range 0 31
|
|
depends on UART_NRF5
|
|
depends on GPIO_NRF5
|
|
depends on UART_NRF5_FLOW_CONTROL
|
|
help
|
|
The GPIO pin to use for CTS.
|