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zephyr/soc
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Charles E. Youse 3bc79fdf2c arch/x86: refactor APIC timer configuration to SoC level 
The APIC is part of the SoC, not the board, so move the defaults down.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-21 16:43:26 -07:00
..
arc
arm arm: v2m_musca: Enable GPIO support 2019-09-20 10:05:18 -05:00
nios2
posix
riscv linker: cxx: Include .gcc_except_table sections 2019-09-19 09:26:42 -05:00
x86 arch/x86: refactor APIC timer configuration to SoC level 2019-09-21 16:43:26 -07:00
x86_64/x86_64
xtensa linker: cxx: xtensa: Added .gcc_except_table.* 2019-09-19 09:26:42 -05:00
Kconfig