mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-31 09:55:56 +00:00
87dd0492db
Previously, DTS specification of physical RAM bounds did not correspond to the actual bounds of system RAM as the first megabyte was being skipped. There were reasons for this - the first 1MB on PC-like systems is a no-man's-land of reserved memory regions, but we need DTS to accurately capture physical memory bounds. Instead, we introduce a config option which can apply an offset to the beginning of physical memory, and apply this to the "RAM" region defined in the linker scripts. This also fixes a problem where an extra megabyte was being added to the size of system RAM. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
75 lines
1.3 KiB
Plaintext
75 lines
1.3 KiB
Plaintext
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/intel-ioapic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qemu32";
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reg = <0>;
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};
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};
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intc: ioapic@fec00000 {
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compatible = "intel,ioapic";
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reg = <0xfec00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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sram0: memory@0 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x0 DT_SRAM_SIZE>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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label = "UART_0";
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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uart1: uart@2f8 {
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compatible = "ns16550";
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reg = <0x000002f8 0x100>;
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label = "UART_1";
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clock-frequency = <1843200>;
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interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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hpet: hpet@fed00000 {
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label = "HPET";
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compatible = "intel,hpet";
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reg = <0xfed00000 0x400>;
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interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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};
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};
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