Yasushi SHOJI 51bc0a065c linker: Make alignment size for sw_isr_table configurable ... sw_isr_table has two entries, an argument and an ISR function. The comment on struct _isr_table_entry in include/sw_isr_table.h says that "This allows a table entry to be loaded [...] with one ldmia instruction, on ARM [...]". Some arch, e.g. SPARC, also has a double word load instruction, "ldd", but the instruct must have address align to double word or 8 bytes. This commit makes the table alignment configurable. It allows each architecture to specify it, if needed. The default value is 0 for no alignment. Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>		2019-07-24 10:09:02 -07:00
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app_smem_aligned.ld
app_smem_unaligned.ld
app_smem.ld
common-ram.ld	linker: Make alignment size for sw_isr_table configurable	2019-07-24 10:09:02 -07:00
common-rom.ld	linker: Make alignment size for sw_isr_table configurable	2019-07-24 10:09:02 -07:00
debug-sections.ld
intlist.ld
kobject-rom.ld
kobject-text.ld
kobject.ld
linker-defs.h	linker: Add dtcm section for Cortex M7 MCUs	2019-07-19 10:05:46 +02:00
linker-tool-gcc.h
linker-tool.h
priv_stacks-noinit.ld
priv_stacks-rom.ld
priv_stacks-text.ld
priv_stacks.ld
rel-sections.ld
section_tags.h	linker: Add dtcm section for Cortex M7 MCUs	2019-07-19 10:05:46 +02:00
sections.h	linker: Add dtcm section for Cortex M7 MCUs	2019-07-19 10:05:46 +02:00