mirror of
https://github.com/zephyrproject-rtos/zephyr
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57e80e5345
We have been combining imported mcux drivers into a flattened directory structure to maximize driver reuse, but the introduction of additional nxp soc families (lpc and imx) to zephyr has introduced driver naming conflicts. This caused us to rename and modify imported files, such as fsl_gpio.c/h, to make them unique across all three nxp soc families. This makes updating the the mcux drivers complicated, especially for the lpc family. Reoganize the mcux drivers into soc family subfolders, so we can just copy all the drivers from an mcux distribution (which is done on an soc-basis) into the appropriate soc family folder. Undo all of the naming changes that occurred when lpc and imx drivers were originally imported. Undo the accidental squashing of the kinetis watchdog and dcdc drivers that occurred when the imx drivers were introduced. The drawback to this approach is that we have duplicate files when the same hw ip modules exist in multiple soc families, however there are only few cases where this occurs, such as fsl_lpuart and fsl_trng. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
327 lines
8.7 KiB
C
327 lines
8.7 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <gpio.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include <fsl_gpio.h>
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#include "gpio_utils.h"
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struct mcux_igpio_config {
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GPIO_Type *base;
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};
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struct mcux_igpio_data {
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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/* pin callback routine enable flags, by pin number */
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u32_t pin_callback_enables;
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};
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static int mcux_igpio_configure(struct device *dev,
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int access_op, u32_t pin, int flags)
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{
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const struct mcux_igpio_config *config = dev->config->config_info;
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gpio_pin_config_t pin_config;
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u32_t i;
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/* Check for an invalid pin configuration */
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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return -EINVAL;
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}
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pin_config.direction = ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN)
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? kGPIO_DigitalInput : kGPIO_DigitalOutput;
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pin_config.outputLogic = 0;
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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pin_config.interruptMode = kGPIO_IntRisingEdge;
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} else if (flags & GPIO_INT_DOUBLE_EDGE) {
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pin_config.interruptMode =
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kGPIO_IntRisingOrFallingEdge;
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} else {
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pin_config.interruptMode =
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kGPIO_IntFallingEdge;
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}
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} else { /* GPIO_INT_LEVEL */
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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pin_config.interruptMode = kGPIO_IntHighLevel;
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} else {
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pin_config.interruptMode = kGPIO_IntLowLevel;
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}
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}
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} else {
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pin_config.interruptMode = kGPIO_NoIntmode;
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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GPIO_PinInit(config->base, pin, &pin_config);
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} else { /* GPIO_ACCESS_BY_PORT */
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for (i = 0; i < 32; i++) {
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GPIO_PinInit(config->base, i, &pin_config);
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}
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}
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return 0;
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}
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static int mcux_igpio_write(struct device *dev,
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int access_op, u32_t pin, u32_t value)
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{
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const struct mcux_igpio_config *config = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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GPIO_PinWrite(config->base, pin, value);
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} else { /* GPIO_ACCESS_BY_PORT */
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config->base->DR = value;
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}
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return 0;
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}
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static int mcux_igpio_read(struct device *dev,
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int access_op, u32_t pin, u32_t *value)
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{
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const struct mcux_igpio_config *config = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = GPIO_PinRead(config->base, pin);
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} else { /* GPIO_ACCESS_BY_PORT */
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*value = config->base->DR;
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}
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return 0;
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}
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static int mcux_igpio_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct mcux_igpio_data *data = dev->driver_data;
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_gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static int mcux_igpio_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct mcux_igpio_config *config = dev->config->config_info;
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struct mcux_igpio_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables |= BIT(pin);
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GPIO_PortEnableInterrupts(config->base, BIT(pin));
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} else {
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data->pin_callback_enables = 0xFFFFFFFF;
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GPIO_PortEnableInterrupts(config->base, 0xFFFFFFFF);
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}
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return 0;
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}
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static int mcux_igpio_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct mcux_igpio_config *config = dev->config->config_info;
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struct mcux_igpio_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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GPIO_PortDisableInterrupts(config->base, BIT(pin));
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data->pin_callback_enables &= ~BIT(pin);
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} else {
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GPIO_PortDisableInterrupts(config->base, 0);
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data->pin_callback_enables = 0;
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}
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return 0;
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}
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static void mcux_igpio_port_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct mcux_igpio_config *config = dev->config->config_info;
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struct mcux_igpio_data *data = dev->driver_data;
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u32_t enabled_int, int_flags;
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int_flags = GPIO_PortGetInterruptFlags(config->base);
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enabled_int = int_flags & data->pin_callback_enables;
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_gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
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GPIO_ClearPinsInterruptFlags(config->base, enabled_int);
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}
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static const struct gpio_driver_api mcux_igpio_driver_api = {
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.config = mcux_igpio_configure,
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.write = mcux_igpio_write,
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.read = mcux_igpio_read,
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.manage_callback = mcux_igpio_manage_callback,
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.enable_callback = mcux_igpio_enable_callback,
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.disable_callback = mcux_igpio_disable_callback,
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};
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#ifdef CONFIG_GPIO_MCUX_IGPIO_1
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static int mcux_igpio_1_init(struct device *dev);
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static const struct mcux_igpio_config mcux_igpio_1_config = {
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.base = (GPIO_Type *)CONFIG_MCUX_IGPIO_1_BASE_ADDRESS,
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};
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static struct mcux_igpio_data mcux_igpio_1_data;
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DEVICE_AND_API_INIT(mcux_igpio_1, CONFIG_MCUX_IGPIO_1_NAME,
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mcux_igpio_1_init,
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&mcux_igpio_1_data, &mcux_igpio_1_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&mcux_igpio_driver_api);
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static int mcux_igpio_1_init(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_1_IRQ_0, CONFIG_MCUX_IGPIO_1_IRQ_0_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_1), 0);
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irq_enable(CONFIG_MCUX_IGPIO_1_IRQ_0);
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_1_IRQ_1, CONFIG_MCUX_IGPIO_1_IRQ_1_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_1), 0);
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irq_enable(CONFIG_MCUX_IGPIO_1_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_MCUX_IGPIO_1 */
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#ifdef CONFIG_GPIO_MCUX_IGPIO_2
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static int mcux_igpio_2_init(struct device *dev);
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static const struct mcux_igpio_config mcux_igpio_2_config = {
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.base = (GPIO_Type *)CONFIG_MCUX_IGPIO_2_BASE_ADDRESS,
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};
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static struct mcux_igpio_data mcux_igpio_2_data;
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DEVICE_AND_API_INIT(mcux_igpio_2, CONFIG_MCUX_IGPIO_2_NAME,
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mcux_igpio_2_init,
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&mcux_igpio_2_data, &mcux_igpio_2_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&mcux_igpio_driver_api);
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static int mcux_igpio_2_init(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_2_IRQ_0, CONFIG_MCUX_IGPIO_2_IRQ_0_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_2), 0);
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irq_enable(CONFIG_MCUX_IGPIO_2_IRQ_0);
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_2_IRQ_1, CONFIG_MCUX_IGPIO_2_IRQ_1_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_2), 0);
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irq_enable(CONFIG_MCUX_IGPIO_2_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_MCUX_IGPIO_2 */
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#ifdef CONFIG_GPIO_MCUX_IGPIO_3
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static int mcux_igpio_3_init(struct device *dev);
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static const struct mcux_igpio_config mcux_igpio_3_config = {
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.base = (GPIO_Type *)CONFIG_MCUX_IGPIO_3_BASE_ADDRESS,
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};
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static struct mcux_igpio_data mcux_igpio_3_data;
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DEVICE_AND_API_INIT(mcux_igpio_3, CONFIG_MCUX_IGPIO_3_NAME,
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mcux_igpio_3_init,
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&mcux_igpio_3_data, &mcux_igpio_3_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&mcux_igpio_driver_api);
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static int mcux_igpio_3_init(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_3_IRQ_0, CONFIG_MCUX_IGPIO_3_IRQ_0_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_3), 0);
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irq_enable(CONFIG_MCUX_IGPIO_3_IRQ_0);
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_3_IRQ_1, CONFIG_MCUX_IGPIO_3_IRQ_1_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_3), 0);
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irq_enable(CONFIG_MCUX_IGPIO_3_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_MCUX_IGPIO_3 */
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#ifdef CONFIG_GPIO_MCUX_IGPIO_4
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static int mcux_igpio_4_init(struct device *dev);
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static const struct mcux_igpio_config mcux_igpio_4_config = {
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.base = (GPIO_Type *)CONFIG_MCUX_IGPIO_4_BASE_ADDRESS,
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};
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static struct mcux_igpio_data mcux_igpio_4_data;
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DEVICE_AND_API_INIT(mcux_igpio_4, CONFIG_MCUX_IGPIO_4_NAME,
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mcux_igpio_4_init,
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&mcux_igpio_4_data, &mcux_igpio_4_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&mcux_igpio_driver_api);
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static int mcux_igpio_4_init(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_4_IRQ_0, CONFIG_MCUX_IGPIO_4_IRQ_0_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_4), 0);
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irq_enable(CONFIG_MCUX_IGPIO_4_IRQ_0);
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_4_IRQ_1, CONFIG_MCUX_IGPIO_4_IRQ_1_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_4), 0);
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irq_enable(CONFIG_MCUX_IGPIO_4_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_MCUX_IGPIO_4 */
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#ifdef CONFIG_GPIO_MCUX_IGPIO_5
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static int mcux_igpio_5_init(struct device *dev);
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static const struct mcux_igpio_config mcux_igpio_5_config = {
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.base = (GPIO_Type *)CONFIG_MCUX_IGPIO_5_BASE_ADDRESS,
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};
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static struct mcux_igpio_data mcux_igpio_5_data;
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DEVICE_AND_API_INIT(mcux_igpio_5, CONFIG_MCUX_IGPIO_5_NAME,
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mcux_igpio_5_init,
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&mcux_igpio_5_data, &mcux_igpio_5_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&mcux_igpio_driver_api);
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static int mcux_igpio_5_init(struct device *dev)
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{
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_5_IRQ_0, CONFIG_MCUX_IGPIO_5_IRQ_0_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0);
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irq_enable(CONFIG_MCUX_IGPIO_5_IRQ_0);
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IRQ_CONNECT(CONFIG_MCUX_IGPIO_5_IRQ_1, CONFIG_MCUX_IGPIO_5_IRQ_1_PRI,
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mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0);
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irq_enable(CONFIG_MCUX_IGPIO_5_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_MCUX_IGPIO_5 */
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