mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-03 05:43:45 +00:00
4dcfb5531c
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs
This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.
Note that only the ISR passed to IRQ_CONNECT are of interest here.
In order to do so, the script fix_isr.py below is necessary:
from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os
cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
...
(
const struct device *D = (const struct device *)P;
|
const struct device *D = P;
)
...
}
@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
...
const struct device *D;
...
(
D = (const struct device *)P;
|
D = P;
)
...
}
@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
...
}
@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);
@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
...
}
@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
...
}
"""
def find_isr(fn):
db = []
data = None
start = 0
try:
with open(fn, 'r+') as f:
data = str(mmap.mmap(f.fileno(), 0).read())
except Exception as e:
return db
while True:
isr = ""
irq = data.find('IRQ_CONNECT', start)
while irq > -1:
p = 1
arg = 1
p_o = data.find('(', irq)
if p_o < 0:
irq = -1
break;
pos = p_o + 1
while p > 0:
if data[pos] == ')':
p -= 1
elif data[pos] == '(':
p += 1
elif data[pos] == ',' and p == 1:
arg += 1
if arg == 3:
isr += data[pos]
pos += 1
isr = isr.strip(',\\n\\t ')
if isr not in db and len(isr) > 0:
db.append(isr)
start = pos
break
if irq < 0:
break
return db
def patch_isr(fn, isr_list):
if len(isr_list) <= 0:
return
for isr in isr_list:
tmplt = cocci_template.replace('<!fn!>', isr)
with open('/tmp/isr_fix.cocci', 'w') as f:
f.write(tmplt)
cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]
subprocess.run(cmd)
def process_files(path):
if path.is_file() and path.suffix in ['.h', '.c']:
p = str(path.parent) + '/' + path.name
isr_list = find_isr(p)
patch_isr(p, isr_list)
elif path.is_dir():
for p in path.iterdir():
process_files(p)
if len(sys.argv) < 2:
print("You need to provide a dir/file path")
sys.exit(1)
process_files(Path(sys.argv[1]))
And is run: ./fix_isr.py <zephyr root directory>
Finally, some files needed manual fixes such.
Fixes #27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
220 lines
5.1 KiB
C
220 lines
5.1 KiB
C
/*
|
|
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
|
|
* Contributors: 2018 Antmicro <www.antmicro.com>
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#define DT_DRV_COMPAT sifive_plic_1_0_0
|
|
|
|
/**
|
|
* @brief Platform Level Interrupt Controller (PLIC) driver
|
|
* for RISC-V processors
|
|
*/
|
|
|
|
#include <kernel.h>
|
|
#include <arch/cpu.h>
|
|
#include <init.h>
|
|
#include <soc.h>
|
|
|
|
#include <sw_isr_table.h>
|
|
|
|
#define PLIC_MAX_PRIO DT_INST_PROP(0, riscv_max_priority)
|
|
#define PLIC_PRIO DT_INST_REG_ADDR_BY_NAME(0, prio)
|
|
#define PLIC_IRQ_EN DT_INST_REG_ADDR_BY_NAME(0, irq_en)
|
|
#define PLIC_REG DT_INST_REG_ADDR_BY_NAME(0, reg)
|
|
|
|
#define PLIC_IRQS (CONFIG_NUM_IRQS - CONFIG_2ND_LVL_ISR_TBL_OFFSET)
|
|
#define PLIC_EN_SIZE ((PLIC_IRQS >> 5) + 1)
|
|
|
|
struct plic_regs_t {
|
|
uint32_t threshold_prio;
|
|
uint32_t claim_complete;
|
|
};
|
|
|
|
static int save_irq;
|
|
|
|
/**
|
|
*
|
|
* @brief Enable a riscv PLIC-specific interrupt line
|
|
*
|
|
* This routine enables a RISCV PLIC-specific interrupt line.
|
|
* riscv_plic_irq_enable is called by SOC_FAMILY_RISCV_PRIVILEGE
|
|
* arch_irq_enable function to enable external interrupts for
|
|
* IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
|
|
* @param irq IRQ number to enable
|
|
*
|
|
* @return N/A
|
|
*/
|
|
void riscv_plic_irq_enable(uint32_t irq)
|
|
{
|
|
uint32_t key;
|
|
volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
|
|
|
|
key = irq_lock();
|
|
en += (irq >> 5);
|
|
*en |= (1 << (irq & 31));
|
|
irq_unlock(key);
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Disable a riscv PLIC-specific interrupt line
|
|
*
|
|
* This routine disables a RISCV PLIC-specific interrupt line.
|
|
* riscv_plic_irq_disable is called by SOC_FAMILY_RISCV_PRIVILEGE
|
|
* arch_irq_disable function to disable external interrupts, for
|
|
* IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
|
|
* @param irq IRQ number to disable
|
|
*
|
|
* @return N/A
|
|
*/
|
|
void riscv_plic_irq_disable(uint32_t irq)
|
|
{
|
|
uint32_t key;
|
|
volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
|
|
|
|
key = irq_lock();
|
|
en += (irq >> 5);
|
|
*en &= ~(1 << (irq & 31));
|
|
irq_unlock(key);
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Check if a riscv PLIC-specific interrupt line is enabled
|
|
*
|
|
* This routine checks if a RISCV PLIC-specific interrupt line is enabled.
|
|
* @param irq IRQ number to check
|
|
*
|
|
* @return 1 or 0
|
|
*/
|
|
int riscv_plic_irq_is_enabled(uint32_t irq)
|
|
{
|
|
volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
|
|
|
|
en += (irq >> 5);
|
|
return !!(*en & (1 << (irq & 31)));
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Set priority of a riscv PLIC-specific interrupt line
|
|
*
|
|
* This routine set the priority of a RISCV PLIC-specific interrupt line.
|
|
* riscv_plic_irq_set_prio is called by riscv arch_irq_priority_set to set
|
|
* the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set.
|
|
* @param irq IRQ number for which to set priority
|
|
*
|
|
* @return N/A
|
|
*/
|
|
void riscv_plic_set_priority(uint32_t irq, uint32_t priority)
|
|
{
|
|
volatile uint32_t *prio = (volatile uint32_t *)PLIC_PRIO;
|
|
|
|
if (priority > PLIC_MAX_PRIO)
|
|
priority = PLIC_MAX_PRIO;
|
|
|
|
prio += irq;
|
|
*prio = priority;
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Get riscv PLIC-specific interrupt line causing an interrupt
|
|
*
|
|
* This routine returns the RISCV PLIC-specific interrupt line causing an
|
|
* interrupt.
|
|
* @param irq IRQ number for which to set priority
|
|
*
|
|
* @return N/A
|
|
*/
|
|
int riscv_plic_get_irq(void)
|
|
{
|
|
return save_irq;
|
|
}
|
|
|
|
static void plic_irq_handler(const void *arg)
|
|
{
|
|
volatile struct plic_regs_t *regs =
|
|
(volatile struct plic_regs_t *) PLIC_REG;
|
|
|
|
uint32_t irq;
|
|
struct _isr_table_entry *ite;
|
|
|
|
/* Get the IRQ number generating the interrupt */
|
|
irq = regs->claim_complete;
|
|
|
|
/*
|
|
* Save IRQ in save_irq. To be used, if need be, by
|
|
* subsequent handlers registered in the _sw_isr_table table,
|
|
* as IRQ number held by the claim_complete register is
|
|
* cleared upon read.
|
|
*/
|
|
save_irq = irq;
|
|
|
|
/*
|
|
* If the IRQ is out of range, call z_irq_spurious.
|
|
* A call to z_irq_spurious will not return.
|
|
*/
|
|
if (irq == 0U || irq >= PLIC_IRQS)
|
|
z_irq_spurious(NULL);
|
|
|
|
irq += CONFIG_2ND_LVL_ISR_TBL_OFFSET;
|
|
|
|
/* Call the corresponding IRQ handler in _sw_isr_table */
|
|
ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
|
|
ite->isr(ite->arg);
|
|
|
|
/*
|
|
* Write to claim_complete register to indicate to
|
|
* PLIC controller that the IRQ has been handled.
|
|
*/
|
|
regs->claim_complete = save_irq;
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Initialize the Platform Level Interrupt Controller
|
|
* @return N/A
|
|
*/
|
|
static int plic_init(const struct device *dev)
|
|
{
|
|
ARG_UNUSED(dev);
|
|
|
|
volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
|
|
volatile uint32_t *prio = (volatile uint32_t *)PLIC_PRIO;
|
|
volatile struct plic_regs_t *regs =
|
|
(volatile struct plic_regs_t *)PLIC_REG;
|
|
int i;
|
|
|
|
/* Ensure that all interrupts are disabled initially */
|
|
for (i = 0; i < PLIC_EN_SIZE; i++) {
|
|
*en = 0U;
|
|
en++;
|
|
}
|
|
|
|
/* Set priority of each interrupt line to 0 initially */
|
|
for (i = 0; i < PLIC_IRQS; i++) {
|
|
*prio = 0U;
|
|
prio++;
|
|
}
|
|
|
|
/* Set threshold priority to 0 */
|
|
regs->threshold_prio = 0U;
|
|
|
|
/* Setup IRQ handler for PLIC driver */
|
|
IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
|
|
0,
|
|
plic_irq_handler,
|
|
NULL,
|
|
0);
|
|
|
|
/* Enable IRQ for PLIC driver */
|
|
irq_enable(RISCV_MACHINE_EXT_IRQ);
|
|
|
|
return 0;
|
|
}
|
|
|
|
SYS_INIT(plic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|