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zephyr/drivers/interrupt_controller/intc_rv32m1_intmux.c
Tomasz Bursztyka 4dcfb5531c isr: Normalize usage of device instance through ISR 
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs

This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.

Note that only the ISR passed to IRQ_CONNECT are of interest here.

In order to do so, the script fix_isr.py below is necessary:

from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os

cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
(
 const struct device *D = (const struct device *)P;
|
 const struct device *D = P;
)
 ...
}

@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
 ...
 const struct device *D;
 ...
(
 D = (const struct device *)P;
|
 D = P;
)
 ...
}

@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
 ...
}

@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);

@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
 ...
}

@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
 ...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
 ...
}
"""

def find_isr(fn):
    db = []
    data = None
    start = 0

    try:
        with open(fn, 'r+') as f:
            data = str(mmap.mmap(f.fileno(), 0).read())
    except Exception as e:
        return db

    while True:
        isr = ""
        irq = data.find('IRQ_CONNECT', start)
        while irq > -1:
            p = 1
            arg = 1
            p_o = data.find('(', irq)
            if p_o < 0:
                irq = -1
                break;

            pos = p_o + 1

            while p > 0:
                if data[pos] == ')':
                    p -= 1
                elif data[pos] == '(':
                    p += 1
                elif data[pos] == ',' and p == 1:
                    arg += 1

                if arg == 3:
                    isr += data[pos]

                pos += 1

            isr = isr.strip(',\\n\\t ')
            if isr not in db and len(isr) > 0:
                db.append(isr)

            start = pos
            break

        if irq < 0:
            break

    return db

def patch_isr(fn, isr_list):
    if len(isr_list) <= 0:
        return

    for isr in isr_list:
        tmplt = cocci_template.replace('<!fn!>', isr)
        with open('/tmp/isr_fix.cocci', 'w') as f:
            f.write(tmplt)

        cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]

        subprocess.run(cmd)

def process_files(path):
    if path.is_file() and path.suffix in ['.h', '.c']:
        p = str(path.parent) + '/' + path.name
        isr_list = find_isr(p)
        patch_isr(p, isr_list)
    elif path.is_dir():
        for p in path.iterdir():
            process_files(p)

if len(sys.argv) < 2:
    print("You need to provide a dir/file path")
    sys.exit(1)

process_files(Path(sys.argv[1]))

And is run: ./fix_isr.py <zephyr root directory>

Finally, some files needed manual fixes such.

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00

227 lines
6.0 KiB
C
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/*
* Copyright (c) 2018 Foundries.io
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT openisa_rv32m1_intmux
/**
* @file
* @brief RV32M1 INTMUX (interrupt multiplexer) driver
*
* This driver provides support for level 2 interrupts on the RV32M1
* SoC using the INTMUX peripheral.
*
* Each of the RI5CY and ZERO-RISCY cores has an INTMUX peripheral;
* INTMUX0 is wired to the RI5CY event unit interrupt table, while
* INTMUX1 is used with ZERO-RISCY.
*
* For this reason, only a single intmux device is declared here. The
* dtsi for each core needs to set up the intmux device and any
* associated IRQ numbers to work with this driver.
*/
#include <kernel.h>
#include <drivers/clock_control.h>
#include <init.h>
#include <irq.h>
#include <irq_nextlevel.h>
#include <sw_isr_table.h>
#include <soc.h>
#include <dt-bindings/interrupt-controller/openisa-intmux.h>
/*
* CHn_VEC registers are offset by a value that is convenient if
* you're dealing with a Cortex-M NVIC vector table; we're not, so it
* needs to be subtracted out to get a useful value.
*/
#define VECN_OFFSET 48U
struct rv32m1_intmux_config {
INTMUX_Type *regs;
char *clock_name;
clock_control_subsys_t clock_subsys;
struct _isr_table_entry *isr_base;
};
#define DEV_CFG(dev) \
((struct rv32m1_intmux_config *)(dev->config))
#define DEV_REGS(dev) (DEV_CFG(dev)->regs)
DEVICE_DECLARE(intmux);
/*
* <irq_nextlevel.h> API
*/
static void rv32m1_intmux_irq_enable(const struct device *dev, uint32_t irq)
{
INTMUX_Type *regs = DEV_REGS(dev);
uint32_t channel = rv32m1_intmux_channel(irq);
uint32_t line = rv32m1_intmux_line(irq);
regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line);
}
static void rv32m1_intmux_irq_disable(const struct device *dev, uint32_t irq)
{
INTMUX_Type *regs = DEV_REGS(dev);
uint32_t channel = rv32m1_intmux_channel(irq);
uint32_t line = rv32m1_intmux_line(irq);
regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line);
}
static uint32_t rv32m1_intmux_get_state(const struct device *dev)
{
INTMUX_Type *regs = DEV_REGS(dev);
size_t i;
for (i = 0; i < INTMUX_CHn_IER_31_0_COUNT; i++) {
if (regs->CHANNEL[i].CHn_IER_31_0) {
return 1;
}
}
return 0;
}
static int rv32m1_intmux_get_line_state(const struct device *dev,
unsigned int irq)
{
INTMUX_Type *regs = DEV_REGS(dev);
uint32_t channel = rv32m1_intmux_channel(irq);
uint32_t line = rv32m1_intmux_line(irq);
if ((regs->CHANNEL[channel].CHn_IER_31_0 & BIT(line)) != 0) {
return 1;
}
return 0;
}
/*
* IRQ handling.
*/
#define ISR_ENTRY(channel, line) \
((channel) * CONFIG_MAX_IRQ_PER_AGGREGATOR + line)
static void rv32m1_intmux_isr(const void *arg)
{
const struct device *dev = DEVICE_GET(intmux);
INTMUX_Type *regs = DEV_REGS(dev);
uint32_t channel = POINTER_TO_UINT(arg);
uint32_t line = (regs->CHANNEL[channel].CHn_VEC >> 2);
struct _isr_table_entry *isr_base = DEV_CFG(dev)->isr_base;
struct _isr_table_entry *entry;
/*
* Make sure the vector is valid, there is a note of page 1243~1244
* of chapter 36 INTMUX of RV32M1 RM,
* Note: Unlike the NVIC, the INTMUX does not latch pending source
* interrupts. This means that the INTMUX output channel ISRs must
* check for and handle a 0 value of the CHn_VEC register to
* account for spurious interrupts.
*/
if (line < VECN_OFFSET) {
return;
}
entry = &isr_base[ISR_ENTRY(channel, (line - VECN_OFFSET))];
entry->isr(entry->arg);
}
/*
* Instance and initialization
*/
static const struct irq_next_level_api rv32m1_intmux_apis = {
.intr_enable = rv32m1_intmux_irq_enable,
.intr_disable = rv32m1_intmux_irq_disable,
.intr_get_state = rv32m1_intmux_get_state,
.intr_get_line_state = rv32m1_intmux_get_line_state,
};
static const struct rv32m1_intmux_config rv32m1_intmux_cfg = {
.regs = (INTMUX_Type *)DT_INST_REG_ADDR(0),
.clock_name = DT_INST_CLOCKS_LABEL(0),
.clock_subsys = UINT_TO_POINTER(DT_INST_CLOCKS_CELL(0, name)),
.isr_base = &_sw_isr_table[CONFIG_2ND_LVL_ISR_TBL_OFFSET],
};
static int rv32m1_intmux_init(const struct device *dev)
{
const struct rv32m1_intmux_config *config = DEV_CFG(dev);
INTMUX_Type *regs = DEV_REGS(dev);
const struct device *clock_dev = device_get_binding(config->clock_name);
size_t i;
if (!clock_dev) {
return -ENODEV;
}
/* Enable INTMUX clock. */
clock_control_on(clock_dev, config->clock_subsys);
/*
* Reset all channels, not just the ones we're configured to
* support. We don't want to continue to take level 2 IRQs
* enabled by bootloaders, for example.
*/
for (i = 0; i < INTMUX_CHn_CSR_COUNT; i++) {
regs->CHANNEL[i].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK;
}
/* Connect and enable level 1 (channel) interrupts. */
#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_0
IRQ_CONNECT(INTMUX_CH0_IRQ, 0, rv32m1_intmux_isr,
UINT_TO_POINTER(0), 0);
irq_enable(INTMUX_CH0_IRQ);
#endif
#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_1
IRQ_CONNECT(INTMUX_CH1_IRQ, 0, rv32m1_intmux_isr,
UINT_TO_POINTER(1), 0);
irq_enable(INTMUX_CH1_IRQ);
#endif
#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_2
IRQ_CONNECT(INTMUX_CH2_IRQ, 0, rv32m1_intmux_isr,
UINT_TO_POINTER(2), 0);
irq_enable(INTMUX_CH2_IRQ);
#endif
#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_3
IRQ_CONNECT(INTMUX_CH3_IRQ, 0, rv32m1_intmux_isr,
UINT_TO_POINTER(3), 0);
irq_enable(INTMUX_CH3_IRQ);
#endif
#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_4
IRQ_CONNECT(INTMUX_CH4_IRQ, 0, rv32m1_intmux_isr,
UINT_TO_POINTER(4), 0);
irq_enable(INTMUX_CH4_IRQ);
#endif
#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_5
IRQ_CONNECT(INTMUX_CH5_IRQ, 0, rv32m1_intmux_isr,
UINT_TO_POINTER(5), 0);
irq_enable(INTMUX_CH5_IRQ);
#endif
#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_6
IRQ_CONNECT(INTMUX_CH6_IRQ, 0, rv32m1_intmux_isr,
UINT_TO_POINTER(6), 0);
irq_enable(INTMUX_CH6_IRQ);
#endif
#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_7
IRQ_CONNECT(INTMUX_CH7_IRQ, 0, rv32m1_intmux_isr,
UINT_TO_POINTER(7), 0);
irq_enable(INTMUX_CH7_IRQ);
#endif
return 0;
}
DEVICE_AND_API_INIT(intmux, DT_INST_LABEL(0),
&rv32m1_intmux_init, NULL,
&rv32m1_intmux_cfg, PRE_KERNEL_1,
CONFIG_RV32M1_INTMUX_INIT_PRIORITY, &rv32m1_intmux_apis);
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