mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-14 02:25:49 +00:00
669a0d6f5b
The default priority for I2C controller initialization is POST_KERNEL 60 (SPI 70), while the default priority for device configuration is POST_KERNEL 50. Thus the EEPROM is being initialized before its controller. While for this driver that wouldn't be an issue recent changes mean the device lookup returns NULL before the device is initialized. Change the AT2X priority to 75 so it falls between the I2C and SPI drivers and the default ethernet priority (80), since some ethernet controllers may store the MAC address in EEPROM. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
627 lines
15 KiB
C
627 lines
15 KiB
C
/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Driver for Atmel AT24 I2C and Atmel AT25 SPI EEPROMs.
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*/
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#include <drivers/eeprom.h>
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#include <drivers/gpio.h>
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#include <drivers/i2c.h>
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#include <drivers/spi.h>
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#include <sys/byteorder.h>
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#include <zephyr.h>
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#define LOG_LEVEL CONFIG_EEPROM_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(eeprom_at2x);
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/* AT25 instruction set */
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#define EEPROM_AT25_WRSR 0x01U /* Write STATUS register */
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#define EEPROM_AT25_WRITE 0x02U /* Write data to memory array */
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#define EEPROM_AT25_READ 0x03U /* Read data from memory array */
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#define EEPROM_AT25_WRDI 0x04U /* Reset the write enable latch */
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#define EEPROM_AT25_RDSR 0x05U /* Read STATUS register */
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#define EEPROM_AT25_WREN 0x06U /* Set the write enable latch */
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/* AT25 status register bits */
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#define EEPROM_AT25_STATUS_WIP BIT(0) /* Write-In-Process (RO) */
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#define EEPROM_AT25_STATUS_WEL BIT(1) /* Write Enable Latch (RO) */
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#define EEPROM_AT25_STATUS_BP0 BIT(2) /* Block Protection 0 (RW) */
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#define EEPROM_AT25_STATUS_BP1 BIT(3) /* Block Protection 1 (RW) */
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struct eeprom_at2x_config {
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const char *bus_dev_name;
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uint16_t bus_addr;
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uint32_t max_freq;
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const char *spi_cs_dev_name;
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gpio_pin_t spi_cs_pin;
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gpio_dt_flags_t spi_cs_dt_flags;
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gpio_pin_t wp_gpio_pin;
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gpio_dt_flags_t wp_gpio_flags;
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const char *wp_gpio_name;
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size_t size;
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size_t pagesize;
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uint8_t addr_width;
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bool readonly;
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uint16_t timeout;
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eeprom_api_read read_fn;
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eeprom_api_write write_fn;
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};
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struct eeprom_at2x_data {
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const struct device *bus_dev;
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#ifdef CONFIG_EEPROM_AT25
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struct spi_config spi_cfg;
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struct spi_cs_control spi_cs;
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#endif /* CONFIG_EEPROM_AT25 */
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const struct device *wp_gpio_dev;
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struct k_mutex lock;
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};
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static inline int eeprom_at2x_write_protect(const struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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if (!data->wp_gpio_dev) {
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return 0;
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}
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return gpio_pin_set(data->wp_gpio_dev, config->wp_gpio_pin, 1);
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}
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static inline int eeprom_at2x_write_enable(const struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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if (!data->wp_gpio_dev) {
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return 0;
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}
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return gpio_pin_set(data->wp_gpio_dev, config->wp_gpio_pin, 0);
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}
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static int eeprom_at2x_read(const struct device *dev, off_t offset, void *buf,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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int err;
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if (!len) {
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return 0;
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}
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if ((offset + len) > config->size) {
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LOG_WRN("attempt to read past device boundary");
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return -EINVAL;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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err = config->read_fn(dev, offset, buf, len);
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k_mutex_unlock(&data->lock);
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if (err) {
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LOG_ERR("failed to read EEPROM (err %d)", err);
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return err;
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}
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return 0;
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}
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static size_t eeprom_at2x_limit_write_count(const struct device *dev,
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off_t offset,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config;
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size_t count = len;
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off_t page_boundary;
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/* We can at most write one page at a time */
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if (count > config->pagesize) {
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count = config->pagesize;
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}
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/* Writes can not cross a page boundary */
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page_boundary = ROUND_UP(offset + 1, config->pagesize);
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if (offset + count > page_boundary) {
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count = page_boundary - offset;
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}
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return count;
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}
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static int eeprom_at2x_write(const struct device *dev, off_t offset,
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const void *buf,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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const uint8_t *pbuf = buf;
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int ret;
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if (config->readonly) {
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LOG_WRN("attempt to write to read-only device");
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return -EACCES;
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}
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if (!len) {
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return 0;
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}
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if ((offset + len) > config->size) {
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LOG_WRN("attempt to write past device boundary");
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return -EINVAL;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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ret = eeprom_at2x_write_enable(dev);
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if (ret) {
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LOG_ERR("failed to write-enable EEPROM (err %d)", ret);
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k_mutex_unlock(&data->lock);
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return ret;
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}
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while (len) {
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ret = config->write_fn(dev, offset, pbuf, len);
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if (ret < 0) {
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LOG_ERR("failed to write to EEPROM (err %d)", ret);
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eeprom_at2x_write_protect(dev);
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k_mutex_unlock(&data->lock);
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return ret;
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}
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pbuf += ret;
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offset += ret;
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len -= ret;
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}
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ret = eeprom_at2x_write_protect(dev);
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if (ret) {
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LOG_ERR("failed to write-protect EEPROM (err %d)", ret);
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}
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k_mutex_unlock(&data->lock);
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return ret;
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}
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static size_t eeprom_at2x_size(const struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config;
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return config->size;
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}
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#ifdef CONFIG_EEPROM_AT24
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static int eeprom_at24_read(const struct device *dev, off_t offset, void *buf,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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int64_t timeout;
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uint8_t addr[2];
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int err;
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if (config->addr_width == 16) {
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sys_put_be16(offset, addr);
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} else {
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addr[0] = offset & BIT_MASK(8);
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}
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/*
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* A write cycle may be in progress so reads must be attempted
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* until the current write cycle should be completed.
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*/
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timeout = k_uptime_get() + config->timeout;
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while (1) {
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int64_t now = k_uptime_get();
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err = i2c_write_read(data->bus_dev, config->bus_addr,
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addr, config->addr_width / 8,
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buf, len);
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if (!err || now > timeout) {
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break;
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}
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k_sleep(K_MSEC(1));
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}
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return err;
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}
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static int eeprom_at24_write(const struct device *dev, off_t offset,
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const void *buf, size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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int count = eeprom_at2x_limit_write_count(dev, offset, len);
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uint8_t block[config->addr_width / 8 + count];
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int64_t timeout;
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int i = 0;
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int err;
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/*
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* Not all I2C EEPROMs support repeated start so the the
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* address (offset) and data (buf) must be provided in one
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* write transaction (block).
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*/
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if (config->addr_width == 16) {
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block[i++] = offset >> 8;
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}
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block[i++] = offset;
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memcpy(&block[i], buf, count);
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/*
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* A write cycle may already be in progress so writes must be
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* attempted until the previous write cycle should be
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* completed.
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*/
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timeout = k_uptime_get() + config->timeout;
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while (1) {
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int64_t now = k_uptime_get();
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err = i2c_write(data->bus_dev, block, sizeof(block),
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config->bus_addr);
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if (!err || now > timeout) {
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break;
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}
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k_sleep(K_MSEC(1));
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}
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if (err < 0) {
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return err;
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}
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return count;
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}
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#endif /* CONFIG_EEPROM_AT24 */
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#ifdef CONFIG_EEPROM_AT25
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static int eeprom_at25_rdsr(const struct device *dev, uint8_t *status)
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{
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struct eeprom_at2x_data *data = dev->data;
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uint8_t rdsr[2] = { EEPROM_AT25_RDSR, 0 };
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uint8_t sr[2];
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int err;
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const struct spi_buf tx_buf = {
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.buf = rdsr,
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.len = sizeof(rdsr),
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_buf = {
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.buf = sr,
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.len = sizeof(sr),
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};
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const struct spi_buf_set rx = {
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.buffers = &rx_buf,
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.count = 1,
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};
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err = spi_transceive(data->bus_dev, &data->spi_cfg, &tx, &rx);
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if (!err) {
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*status = sr[1];
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}
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return err;
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}
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static int eeprom_at25_wait_for_idle(const struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config;
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int64_t timeout;
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uint8_t status;
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int err;
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timeout = k_uptime_get() + config->timeout;
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while (1) {
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int64_t now = k_uptime_get();
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err = eeprom_at25_rdsr(dev, &status);
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if (err) {
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LOG_ERR("Could not read status register (err %d)", err);
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return err;
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}
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if (!(status & EEPROM_AT25_STATUS_WIP)) {
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return 0;
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}
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if (now > timeout) {
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break;
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}
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k_sleep(K_MSEC(1));
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}
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return -EBUSY;
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}
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static int eeprom_at25_read(const struct device *dev, off_t offset, void *buf,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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size_t cmd_len = 1 + config->addr_width / 8;
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uint8_t cmd[4] = { EEPROM_AT25_READ, 0, 0, 0 };
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uint8_t *paddr;
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int err;
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const struct spi_buf tx_buf = {
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.buf = cmd,
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.len = cmd_len,
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_bufs[2] = {
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{
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.buf = NULL,
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.len = cmd_len,
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},
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{
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.buf = buf,
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.len = len,
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},
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};
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const struct spi_buf_set rx = {
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.buffers = rx_bufs,
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.count = ARRAY_SIZE(rx_bufs),
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};
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if (!len) {
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return 0;
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}
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if ((offset + len) > config->size) {
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LOG_WRN("attempt to read past device boundary");
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return -EINVAL;
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}
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paddr = &cmd[1];
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switch (config->addr_width) {
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case 24:
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*paddr++ = offset >> 16;
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__fallthrough;
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case 16:
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*paddr++ = offset >> 8;
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__fallthrough;
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case 8:
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*paddr++ = offset;
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break;
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default:
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__ASSERT(0, "invalid address width");
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}
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err = eeprom_at25_wait_for_idle(dev);
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if (err) {
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LOG_ERR("EEPROM idle wait failed (err %d)", err);
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k_mutex_unlock(&data->lock);
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return err;
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}
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return spi_transceive(data->bus_dev, &data->spi_cfg, &tx, &rx);
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}
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static int eeprom_at25_wren(const struct device *dev)
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{
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struct eeprom_at2x_data *data = dev->data;
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uint8_t cmd = EEPROM_AT25_WREN;
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const struct spi_buf tx_buf = {
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.buf = &cmd,
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.len = 1,
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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return spi_write(data->bus_dev, &data->spi_cfg, &tx);
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}
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static int eeprom_at25_write(const struct device *dev, off_t offset,
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const void *buf, size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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int count = eeprom_at2x_limit_write_count(dev, offset, len);
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uint8_t cmd[4] = { EEPROM_AT25_WRITE, 0, 0, 0 };
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size_t cmd_len = 1 + config->addr_width / 8;
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uint8_t *paddr;
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int err;
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const struct spi_buf tx_bufs[2] = {
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{
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.buf = cmd,
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.len = cmd_len,
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},
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{
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.buf = (void *)buf,
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.len = count,
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},
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};
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const struct spi_buf_set tx = {
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.buffers = tx_bufs,
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.count = ARRAY_SIZE(tx_bufs),
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};
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paddr = &cmd[1];
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switch (config->addr_width) {
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case 24:
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*paddr++ = offset >> 16;
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__fallthrough;
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case 16:
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*paddr++ = offset >> 8;
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__fallthrough;
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case 8:
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*paddr++ = offset;
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break;
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default:
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__ASSERT(0, "invalid address width");
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}
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err = eeprom_at25_wait_for_idle(dev);
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if (err) {
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LOG_ERR("EEPROM idle wait failed (err %d)", err);
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return err;
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}
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err = eeprom_at25_wren(dev);
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if (err) {
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LOG_ERR("failed to disable write protection (err %d)", err);
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return err;
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}
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err = spi_transceive(data->bus_dev, &data->spi_cfg, &tx, NULL);
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if (err) {
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return err;
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}
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return count;
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}
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#endif /* CONFIG_EEPROM_AT25 */
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static int eeprom_at2x_init(const struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config;
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struct eeprom_at2x_data *data = dev->data;
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int err;
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k_mutex_init(&data->lock);
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data->bus_dev = device_get_binding(config->bus_dev_name);
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if (!data->bus_dev) {
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LOG_ERR("could not get parent bus device");
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return -EINVAL;
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}
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#ifdef CONFIG_EEPROM_AT25
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data->spi_cfg.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB |
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SPI_WORD_SET(8);
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data->spi_cfg.frequency = config->max_freq;
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data->spi_cfg.slave = config->bus_addr;
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if (config->spi_cs_dev_name) {
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data->spi_cs.gpio_dev =
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device_get_binding(config->spi_cs_dev_name);
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if (!data->spi_cs.gpio_dev) {
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LOG_ERR("could not get SPI CS GPIO device");
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return -EINVAL;
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}
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data->spi_cs.gpio_pin = config->spi_cs_pin;
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data->spi_cs.gpio_dt_flags = config->spi_cs_dt_flags;
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data->spi_cfg.cs = &data->spi_cs;
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}
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#endif /* CONFIG_EEPROM_AT25 */
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if (config->wp_gpio_name) {
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data->wp_gpio_dev = device_get_binding(config->wp_gpio_name);
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if (!data->wp_gpio_dev) {
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LOG_ERR("could not get WP GPIO device");
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return -EINVAL;
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|
}
|
|
|
|
err = gpio_pin_configure(data->wp_gpio_dev, config->wp_gpio_pin,
|
|
GPIO_OUTPUT_ACTIVE | config->wp_gpio_flags);
|
|
if (err) {
|
|
LOG_ERR("failed to configure WP GPIO pin (err %d)",
|
|
err);
|
|
return err;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eeprom_driver_api eeprom_at2x_api = {
|
|
.read = eeprom_at2x_read,
|
|
.write = eeprom_at2x_write,
|
|
.size = eeprom_at2x_size,
|
|
};
|
|
|
|
#define ASSERT_AT24_ADDR_W_VALID(w) \
|
|
BUILD_ASSERT(w == 8U || w == 16U, \
|
|
"Unsupported address width")
|
|
|
|
#define ASSERT_AT25_ADDR_W_VALID(w) \
|
|
BUILD_ASSERT(w == 8U || w == 16U || w == 24U, \
|
|
"Unsupported address width")
|
|
|
|
#define ASSERT_PAGESIZE_IS_POWER_OF_2(page) \
|
|
BUILD_ASSERT((page != 0U) && ((page & (page - 1)) == 0U), \
|
|
"Page size is not a power of two")
|
|
|
|
#define ASSERT_SIZE_PAGESIZE_VALID(size, page) \
|
|
BUILD_ASSERT(size % page == 0U, \
|
|
"Size is not an integer multiple of page size")
|
|
|
|
#define INST_DT_AT2X(inst, t) DT_INST(inst, atmel_at##t)
|
|
|
|
#define EEPROM_AT2X_DEVICE(n, t) \
|
|
ASSERT_PAGESIZE_IS_POWER_OF_2(DT_PROP(INST_DT_AT2X(n, t), pagesize)); \
|
|
ASSERT_SIZE_PAGESIZE_VALID(DT_PROP(INST_DT_AT2X(n, t), size), \
|
|
DT_PROP(INST_DT_AT2X(n, t), pagesize)); \
|
|
ASSERT_AT##t##_ADDR_W_VALID(DT_PROP(INST_DT_AT2X(n, t), \
|
|
address_width)); \
|
|
static const struct eeprom_at2x_config eeprom_at##t##_config_##n = { \
|
|
.bus_dev_name = DT_BUS_LABEL(INST_DT_AT2X(n, t)), \
|
|
.bus_addr = DT_REG_ADDR(INST_DT_AT2X(n, t)), \
|
|
.max_freq = UTIL_AND( \
|
|
DT_NODE_HAS_PROP(INST_DT_AT2X(n, t), \
|
|
spi_max_frequency), \
|
|
DT_PROP(INST_DT_AT2X(n, t), spi_max_frequency)), \
|
|
.spi_cs_dev_name = UTIL_AND( \
|
|
DT_SPI_DEV_HAS_CS_GPIOS(INST_DT_AT2X(n, t)), \
|
|
DT_SPI_DEV_CS_GPIOS_LABEL(INST_DT_AT2X(n, t))), \
|
|
.spi_cs_pin = UTIL_AND( \
|
|
DT_SPI_DEV_HAS_CS_GPIOS(INST_DT_AT2X(n, t)), \
|
|
DT_SPI_DEV_CS_GPIOS_PIN(INST_DT_AT2X(n, t))), \
|
|
.spi_cs_dt_flags = UTIL_AND( \
|
|
DT_SPI_DEV_HAS_CS_GPIOS(INST_DT_AT2X(n, t)), \
|
|
DT_SPI_DEV_CS_GPIOS_FLAGS(INST_DT_AT2X(n, t))), \
|
|
.wp_gpio_pin = UTIL_AND( \
|
|
DT_NODE_HAS_PROP(INST_DT_AT2X(n, t), wp_gpios), \
|
|
DT_GPIO_PIN(INST_DT_AT2X(n, t), wp_gpios)), \
|
|
.wp_gpio_flags = UTIL_AND( \
|
|
DT_NODE_HAS_PROP(INST_DT_AT2X(n, t), wp_gpios), \
|
|
DT_GPIO_FLAGS(INST_DT_AT2X(n, t), wp_gpios)), \
|
|
.wp_gpio_name = UTIL_AND( \
|
|
DT_NODE_HAS_PROP(INST_DT_AT2X(n, t), wp_gpios), \
|
|
DT_GPIO_LABEL(INST_DT_AT2X(n, t), wp_gpios)), \
|
|
.size = DT_PROP(INST_DT_AT2X(n, t), size), \
|
|
.pagesize = DT_PROP(INST_DT_AT2X(n, t), pagesize), \
|
|
.addr_width = DT_PROP(INST_DT_AT2X(n, t), address_width), \
|
|
.readonly = DT_PROP(INST_DT_AT2X(n, t), read_only), \
|
|
.timeout = DT_PROP(INST_DT_AT2X(n, t), timeout), \
|
|
.read_fn = eeprom_at##t##_read, \
|
|
.write_fn = eeprom_at##t##_write, \
|
|
}; \
|
|
static struct eeprom_at2x_data eeprom_at##t##_data_##n; \
|
|
DEVICE_AND_API_INIT(eeprom_at##t##_##n, \
|
|
DT_LABEL(INST_DT_AT2X(n, t)), \
|
|
&eeprom_at2x_init, &eeprom_at##t##_data_##n, \
|
|
&eeprom_at##t##_config_##n, POST_KERNEL, \
|
|
CONFIG_EEPROM_AT2X_INIT_PRIORITY, \
|
|
&eeprom_at2x_api)
|
|
|
|
#define EEPROM_AT24_DEVICE(n) EEPROM_AT2X_DEVICE(n, 24)
|
|
#define EEPROM_AT25_DEVICE(n) EEPROM_AT2X_DEVICE(n, 25)
|
|
|
|
#define CALL_WITH_ARG(arg, expr) expr(arg);
|
|
|
|
#define INST_DT_AT2X_FOREACH(t, inst_expr) \
|
|
UTIL_LISTIFY(DT_NUM_INST_STATUS_OKAY(atmel_at##t), \
|
|
CALL_WITH_ARG, inst_expr)
|
|
|
|
#ifdef CONFIG_EEPROM_AT24
|
|
INST_DT_AT2X_FOREACH(24, EEPROM_AT24_DEVICE);
|
|
#endif
|
|
|
|
#ifdef CONFIG_EEPROM_AT25
|
|
INST_DT_AT2X_FOREACH(25, EEPROM_AT25_DEVICE);
|
|
#endif
|