mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-31 12:06:17 +00:00
Add support for NVS on the board by default. Using the simulated flash driver is required as this board has no flash controller. Support is desired as this is the ARM board used by coverage testing. Signed-off-by: Jordan Yates <jordan@embeint.com>
285 lines
5.5 KiB
Plaintext
285 lines
5.5 KiB
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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/dts-v1/;
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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compatible = "arm,mps2";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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led0 = &led_0;
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led1 = &led_1;
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sw0 = &user_button_0;
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sw1 = &user_button_1;
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watchdog0 = &wdog0;
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};
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,uart-pipe = &uart1;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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};
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leds {
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compatible = "gpio-leds";
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led_0: led_0 {
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gpios = <&gpio_led0 0>;
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label = "USERLED0";
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};
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led_1: led_1 {
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gpios = <&gpio_led0 1>;
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label = "USERLED1";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_0: button_0 {
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label = "USERPB0";
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gpios = <&gpio_button 0>;
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zephyr,code = <INPUT_KEY_0>;
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};
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user_button_1: button_1 {
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label = "USERPB1";
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gpios = <&gpio_button 1>;
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zephyr,code = <INPUT_KEY_1>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-m3";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 0x400000>;
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};
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 0x400000>;
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};
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sim_flash_controller: sim_flash_controller {
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compatible = "zephyr,sim-flash";
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#address-cells = <1>;
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#size-cells = <1>;
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erase-value = <0x00>;
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flash_sim0: flash_sim@0 {
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compatible = "soc-nv-flash";
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reg = <0x00000000 0x8000>;
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erase-block-size = <1024>;
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write-block-size = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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storage_partition: partition@0 {
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label = "storage_partition";
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reg = <0x00000000 0x8000>;
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};
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};
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};
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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#clock-cells = <0>;
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};
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soc {
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timer0: timer@40000000 {
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compatible = "arm,cmsdk-timer";
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reg = <0x40000000 0x1000>;
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interrupts = <8 3>;
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};
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timer1: timer@40001000 {
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compatible = "arm,cmsdk-timer";
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reg = <0x40001000 0x1000>;
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interrupts = <9 3>;
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};
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dtimer0: dtimer@40002000 {
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compatible = "arm,cmsdk-dtimer";
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reg = <0x40002000 0x1000>;
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interrupts = <10 3>;
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};
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uart0: uart@40004000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40004000 0x1000>;
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interrupts = <1 3 0 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart1: uart@40005000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40005000 0x1000>;
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interrupts = <3 3 2 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart2: uart@40006000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40006000 0x1000>;
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interrupts = <5 3 4 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart3: uart@40007000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40007000 0x1000>;
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interrupts = <19 3 18 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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wdog0: wdog@40008000 {
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compatible = "arm,cmsdk-watchdog";
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clocks = <&sysclk>;
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reg = <0x40008000 0x1000>;
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};
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uart4: uart@40009000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40009000 0x1000>;
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interrupts = <21 3 20 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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gpio0: gpio@40010000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x40010000 0x1000>;
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interrupts = <6 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@40011000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x40011000 0x1000>;
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interrupts = <7 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: gpio@40012000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x40012000 0x1000>;
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interrupts = <16 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio3: gpio@40013000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x40013000 0x1000>;
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interrupts = <17 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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eth0: eth@40200000 {
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/* Linux has "smsc,lan9115" */
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compatible = "smsc,lan9220";
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/* Such a big size from memory map in AN385 */
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/* Actual reg range is ~0x200 */
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reg = <0x40200000 0x100000>;
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interrupts = <13 3>;
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};
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i2c_touch: i2c@40022000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40022000 0x1000>;
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};
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i2c_audio_conf: i2c@40023000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40023000 0x1000>;
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};
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i2c_shield0: i2c@40029000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40029000 0x1000>;
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};
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i2c_shield1: i2c@4002a000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4002a000 0x1000>;
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};
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gpio_led0: mps2_fpgaio@40028000 {
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compatible = "arm,mps2-fpgaio-gpio";
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reg = <0x40028000 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <2>;
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};
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gpio_button: mps2_fpgaio@40028008 {
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compatible = "arm,mps2-fpgaio-gpio";
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reg = <0x40028008 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <2>;
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};
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gpio_misc: mps2_fpgaio@4002804c {
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compatible = "arm,mps2-fpgaio-gpio";
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reg = <0x4002804c 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <10>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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