mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-24 12:16:35 +00:00
bd70f6f1ed
move spi.h to drivers/spi.h and create a shim for backward-compatibility. No functional changes to the headers. A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES. Related to #16539 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
352 lines
9.7 KiB
C
352 lines
9.7 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SENSOR_LIS2DH_LIS2DH_H_
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#define ZEPHYR_DRIVERS_SENSOR_LIS2DH_LIS2DH_H_
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#include <kernel.h>
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#include <device.h>
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#include <misc/util.h>
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#include <stdint.h>
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#include <drivers/gpio.h>
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#include <drivers/sensor.h>
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#include <string.h>
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#define LIS2DH_BUS_ADDRESS DT_INST_0_ST_LIS2DH_BASE_ADDRESS
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#define LIS2DH_BUS_DEV_NAME DT_INST_0_ST_LIS2DH_BUS_NAME
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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#include <drivers/spi.h>
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#define LIS2DH_SPI_READ_BIT BIT(7)
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#define LIS2DH_SPI_AUTOINC_ADDR BIT(6)
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#define LIS2DH_SPI_ADDR_MASK BIT_MASK(6)
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/* LIS2DH supports only SPI mode 0, word size 8 bits, MSB first */
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#define LIS2DH_SPI_CFG SPI_WORD_SET(8)
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#elif defined(DT_ST_LIS2DH_BUS_I2C)
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#include <drivers/i2c.h>
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#else
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#error "define bus type (I2C/SPI)"
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#endif
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#define LIS2DH_AUTOINCREMENT_ADDR BIT(7)
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#define LIS2DH_REG_CTRL1 0x20
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#define LIS2DH_ACCEL_XYZ_SHIFT 0
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#define LIS2DH_ACCEL_X_EN_BIT BIT(0)
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#define LIS2DH_ACCEL_Y_EN_BIT BIT(1)
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#define LIS2DH_ACCEL_Z_EN_BIT BIT(2)
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#define LIS2DH_ACCEL_EN_BITS (LIS2DH_ACCEL_X_EN_BIT | \
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LIS2DH_ACCEL_Y_EN_BIT | \
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LIS2DH_ACCEL_Z_EN_BIT)
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#define LIS2DH_ACCEL_XYZ_MASK BIT_MASK(3)
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#define LIS2DH_LP_EN_BIT_MASK BIT(3)
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#if defined(CONFIG_LIS2DH_POWER_MODE_LOW)
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#define LIS2DH_LP_EN_BIT BIT(3)
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#elif defined(CONFIG_LIS2DH_POWER_MODE_NORMAL)
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#define LIS2DH_LP_EN_BIT 0
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#endif
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#define LIS2DH_ODR_1 1
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#define LIS2DH_ODR_2 2
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#define LIS2DH_ODR_3 3
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#define LIS2DH_ODR_4 4
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#define LIS2DH_ODR_5 5
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#define LIS2DH_ODR_6 6
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#define LIS2DH_ODR_7 7
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#define LIS2DH_ODR_8 8
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#define LIS2DH_ODR_9 9
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#if defined(CONFIG_LIS2DH_ODR_1)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_1
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#elif defined(CONFIG_LIS2DH_ODR_2)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_2
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#elif defined(CONFIG_LIS2DH_ODR_3)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_3
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#elif defined(CONFIG_LIS2DH_ODR_4) || defined(CONFIG_LIS2DH_ODR_RUNTIME)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_4
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#elif defined(CONFIG_LIS2DH_ODR_5)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_5
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#elif defined(CONFIG_LIS2DH_ODR_6)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_6
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#elif defined(CONFIG_LIS2DH_ODR_7)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_7
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#elif defined(CONFIG_LIS2DH_ODR_8)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_8
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#elif defined(CONFIG_LIS2DH_ODR_9_NORMAL) || defined(CONFIG_LIS2DH_ODR_9_LOW)
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#define LIS2DH_ODR_IDX LIS2DH_ODR_9
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#endif
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#define LIS2DH_ODR_SHIFT 4
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#define LIS2DH_ODR_RATE(r) ((r) << LIS2DH_ODR_SHIFT)
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#define LIS2DH_ODR_BITS (LIS2DH_ODR_RATE(LIS2DH_ODR_IDX))
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#define LIS2DH_ODR_MASK (BIT_MASK(4) << LIS2DH_ODR_SHIFT)
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#define LIS2DH_REG_CTRL2 0x21
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#define LIS2DH_HPIS2_EN_BIT BIT(1)
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#define LIS2DH_FDS_EN_BIT BIT(3)
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#define LIS2DH_REG_CTRL3 0x22
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#define LIS2DH_EN_DRDY1_INT1_SHIFT 4
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#define LIS2DH_EN_DRDY1_INT1 BIT(LIS2DH_EN_DRDY1_INT1_SHIFT)
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#define LIS2DH_REG_CTRL4 0x23
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#define LIS2DH_FS_SHIFT 4
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#define LIS2DH_FS_MASK (BIT_MASK(2) << LIS2DH_FS_SHIFT)
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#if defined(CONFIG_LIS2DH_ACCEL_RANGE_2G) ||\
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defined(CONFIG_LIS2DH_ACCEL_RANGE_RUNTIME)
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#define LIS2DH_FS_IDX 0
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#elif defined(CONFIG_LIS2DH_ACCEL_RANGE_4G)
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#define LIS2DH_FS_IDX 1
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#elif defined(CONFIG_LIS2DH_ACCEL_RANGE_8G)
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#define LIS2DH_FS_IDX 2
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#elif defined(CONFIG_LIS2DH_ACCEL_RANGE_16G)
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#define LIS2DH_FS_IDX 3
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#endif
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#define LIS2DH_FS_SELECT(fs) ((fs) << LIS2DH_FS_SHIFT)
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#define LIS2DH_FS_BITS (LIS2DH_FS_SELECT(LIS2DH_FS_IDX))
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#define LIS2DH_ACCEL_SCALE(range_g) ((SENSOR_G * 2 * (range_g)) / 65636LL)
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#define LIS2DH_REG_CTRL5 0x24
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#define LIS2DH_LIR_INT2_SHIFT 1
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#define LIS2DH_EN_LIR_INT2 BIT(LIS2DH_LIR_INT2_SHIFT)
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#define LIS2DH_REG_CTRL6 0x25
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#define LIS2DH_EN_INT2_INT2_SHIFT 5
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#define LIS2DH_EN_INT2_INT2 BIT(LIS2DH_EN_INT2_INT2_SHIFT)
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#define LIS2DH_REG_REFERENCE 0x26
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#define LIS2DH_REG_STATUS 0x27
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#define LIS2DH_STATUS_ZYZ_OVR BIT(7)
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#define LIS2DH_STATUS_Z_OVR BIT(6)
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#define LIS2DH_STATUS_Y_OVR BIT(5)
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#define LIS2DH_STATUS_X_OVR BIT(4)
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#define LIS2DH_STATUS_OVR_MASK (BIT_MASK(4) << 4)
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#define LIS2DH_STATUS_ZYX_DRDY BIT(3)
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#define LIS2DH_STATUS_Z_DRDY BIT(2)
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#define LIS2DH_STATUS_Y_DRDY BIT(1)
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#define LIS2DH_STATUS_X_DRDY BIT(0)
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#define LIS2DH_STATUS_DRDY_MASK BIT_MASK(4)
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#define LIS2DH_REG_ACCEL_X_LSB 0x28
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#define LIS2DH_REG_ACCEL_Y_LSB 0x2A
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#define LIS2DH_REG_ACCEL_Z_LSB 0x2C
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#define LIS2DH_REG_ACCEL_X_MSB 0x29
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#define LIS2DH_REG_ACCEL_Y_MSB 0x2B
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#define LIS2DH_REG_ACCEL_Z_MSB 0x2D
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#define LIS2DH_REG_INT1_CFG 0x30
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#define LIS2DH_REG_INT2_CFG 0x34
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#define LIS2DH_AOI_CFG BIT(7)
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#define LIS2DH_INT_CFG_ZHIE_ZUPE BIT(5)
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#define LIS2DH_INT_CFG_ZLIE_ZDOWNE BIT(4)
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#define LIS2DH_INT_CFG_YHIE_YUPE BIT(3)
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#define LIS2DH_INT_CFG_YLIE_YDOWNE BIT(2)
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#define LIS2DH_INT_CFG_XHIE_XUPE BIT(1)
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#define LIS2DH_INT_CFG_XLIE_XDOWNE BIT(0)
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#define LIS2DH_REG_INT2_SRC 0x35
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#define LIS2DH_REG_INT2_THS 0x36
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#define LIS2DH_REG_INT2_DUR 0x37
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/* sample buffer size includes status register */
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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#define LIS2DH_BUF_SZ 8
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#define LIS2DH_DATA_OFS 1
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#else
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#define LIS2DH_BUF_SZ 7
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#define LIS2DH_DATA_OFS 0
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#endif
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#if defined(DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1)
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/* INT1 and INT2 are configured */
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#define DT_LIS2DH_INT1_GPIOS_PIN DT_INST_0_ST_LIS2DH_IRQ_GPIOS_PIN_0
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#define DT_LIS2DH_INT1_GPIO_DEV_NAME DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_0
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#define DT_LIS2DH_INT2_GPIOS_PIN DT_INST_0_ST_LIS2DH_IRQ_GPIOS_PIN_1
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#define DT_LIS2DH_INT2_GPIO_DEV_NAME DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1
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#else
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/* INT1 only */
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#define DT_LIS2DH_INT1_GPIOS_PIN DT_INST_0_ST_LIS2DH_IRQ_GPIOS_PIN
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#define DT_LIS2DH_INT1_GPIO_DEV_NAME DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER
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#endif
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union lis2dh_sample {
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u8_t raw[LIS2DH_BUF_SZ];
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struct {
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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u8_t dummy;
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#endif
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u8_t status;
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s16_t xyz[3];
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} __packed;
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};
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struct lis2dh_data {
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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struct device *spi;
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struct spi_config spi_cfg;
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#else
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struct device *bus;
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#endif
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union lis2dh_sample sample;
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/* current scaling factor, in micro m/s^2 / lsb */
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u16_t scale;
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#ifdef CONFIG_LIS2DH_TRIGGER
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struct device *gpio_int1;
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struct device *gpio_int2;
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struct gpio_callback gpio_int1_cb;
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struct gpio_callback gpio_int2_cb;
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sensor_trigger_handler_t handler_drdy;
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sensor_trigger_handler_t handler_anymotion;
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atomic_t trig_flags;
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enum sensor_channel chan_drdy;
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#if defined(CONFIG_LIS2DH_TRIGGER_OWN_THREAD)
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K_THREAD_STACK_MEMBER(thread_stack, CONFIG_LIS2DH_THREAD_STACK_SIZE);
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struct k_thread thread;
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struct k_sem gpio_sem;
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#elif defined(CONFIG_LIS2DH_TRIGGER_GLOBAL_THREAD)
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struct k_work work;
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struct device *dev;
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#endif
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#endif /* CONFIG_LIS2DH_TRIGGER */
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};
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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int lis2dh_spi_access(struct lis2dh_data *ctx, u8_t cmd,
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void *data, size_t length);
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#endif
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static inline int lis2dh_bus_configure(struct device *dev)
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{
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struct lis2dh_data *lis2dh = dev->driver_data;
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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lis2dh->spi = device_get_binding(LIS2DH_BUS_DEV_NAME);
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if (lis2dh->spi == NULL) {
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LOG_ERR("Could not get pointer to %s device",
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LIS2DH_BUS_DEV_NAME);
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return -EINVAL;
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}
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lis2dh->spi_cfg.operation = LIS2DH_SPI_CFG;
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lis2dh->spi_cfg.frequency = DT_INST_0_ST_LIS2DH_SPI_MAX_FREQUENCY;
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lis2dh->spi_cfg.slave = LIS2DH_BUS_ADDRESS;
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return 0;
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#elif defined(DT_ST_LIS2DH_BUS_I2C)
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lis2dh->bus = device_get_binding(LIS2DH_BUS_DEV_NAME);
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if (lis2dh->bus == NULL) {
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LOG_ERR("Could not get pointer to %s device",
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LIS2DH_BUS_DEV_NAME);
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return -EINVAL;
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}
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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static inline int lis2dh_burst_read(struct device *dev, u8_t start_addr,
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u8_t *buf, u8_t num_bytes)
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{
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struct lis2dh_data *lis2dh = dev->driver_data;
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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start_addr |= LIS2DH_SPI_READ_BIT | LIS2DH_SPI_AUTOINC_ADDR;
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return lis2dh_spi_access(lis2dh, start_addr, buf, num_bytes);
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#elif defined(DT_ST_LIS2DH_BUS_I2C)
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return i2c_burst_read(lis2dh->bus, LIS2DH_BUS_ADDRESS,
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start_addr | LIS2DH_AUTOINCREMENT_ADDR,
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buf, num_bytes);
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#else
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return -ENODEV;
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#endif
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}
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static inline int lis2dh_reg_read_byte(struct device *dev, u8_t reg_addr,
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u8_t *value)
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{
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struct lis2dh_data *lis2dh = dev->driver_data;
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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reg_addr |= LIS2DH_SPI_READ_BIT;
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return lis2dh_spi_access(lis2dh, reg_addr, value, 1);
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#elif defined(DT_ST_LIS2DH_BUS_I2C)
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return i2c_reg_read_byte(lis2dh->bus, LIS2DH_BUS_ADDRESS,
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reg_addr, value);
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#else
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return -ENODEV;
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#endif
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}
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static inline int lis2dh_burst_write(struct device *dev, u8_t start_addr,
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u8_t *buf, u8_t num_bytes)
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{
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struct lis2dh_data *lis2dh = dev->driver_data;
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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start_addr |= LIS2DH_SPI_AUTOINC_ADDR;
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return lis2dh_spi_access(lis2dh, start_addr, buf, num_bytes);
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#elif defined(DT_ST_LIS2DH_BUS_I2C)
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return i2c_burst_write(lis2dh->bus, LIS2DH_BUS_ADDRESS,
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start_addr | LIS2DH_AUTOINCREMENT_ADDR,
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buf, num_bytes);
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#else
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return -ENODEV;
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#endif
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}
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static inline int lis2dh_reg_write_byte(struct device *dev, u8_t reg_addr,
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u8_t value)
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{
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struct lis2dh_data *lis2dh = dev->driver_data;
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#if defined(DT_ST_LIS2DH_BUS_SPI)
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reg_addr &= LIS2DH_SPI_ADDR_MASK;
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return lis2dh_spi_access(lis2dh, reg_addr, &value, 1);
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#elif defined(DT_ST_LIS2DH_BUS_I2C)
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u8_t tx_buf[2] = {reg_addr, value};
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return i2c_write(lis2dh->bus, tx_buf, sizeof(tx_buf),
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LIS2DH_BUS_ADDRESS);
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#else
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return -ENODEV;
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#endif
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}
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#ifdef CONFIG_LIS2DH_TRIGGER
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int lis2dh_trigger_set(struct device *dev,
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const struct sensor_trigger *trig,
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sensor_trigger_handler_t handler);
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int lis2dh_init_interrupt(struct device *dev);
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int lis2dh_reg_field_update(struct device *dev, u8_t reg_addr,
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u8_t pos, u8_t mask, u8_t val);
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int lis2dh_acc_slope_config(struct device *dev, enum sensor_attribute attr,
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const struct sensor_value *val);
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#endif
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#endif /* __SENSOR_LIS2DH__ */
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