mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-31 19:36:16 +00:00
0e4a5ac6cb
There is no such thing as associating a compatible to a child binding so remove this from the nxp,dmic binding definition and devicetree files that incorrectly set one. Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
575 lines
12 KiB
Plaintext
575 lines
12 KiB
Plaintext
/*
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* Copyright 2022-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/power/nxp_rw_pmu.h>
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#include <dt-bindings/adc/nxp,gau-adc.h>
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#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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/ {
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chosen {
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zephyr,entropy = &trng;
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zephyr,nbu = &nbu;
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zephyr,bt-hci = &hci;
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zephyr,hdlc-rcp-if = &hdlc_rcp_if;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpu-power-states = <&idle &suspend>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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power-states {
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/* Idle mode maps to Power Mode 1 */
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idle: idle {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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min-residency-us = <0>;
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exit-latency-us = <0>;
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};
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/* Suspend mode maps to Power Mode 2 */
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suspend: suspend {
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compatible = "nxp,pdcfg-power", "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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min-residency-us = <500>;
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exit-latency-us = <120>;
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deep-sleep-config = <0x180000>,
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<0x0>,
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<0x4>,
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<0x100>,
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<0x0>;
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};
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};
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};
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smu1: sram@41380000 {
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ranges = <0x0 0x41380000 DT_SIZE_K(510)>;
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};
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smu2: sram@443C0000 {
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ranges = <0x0 0x443C0000 DT_SIZE_K(140)>;
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};
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};
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&sram {
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#address-cells = <1>;
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#size-cells = <1>;
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/* RW6XX SRAM can be access by either code or data bus, determined
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* by the address used to access the memory.
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* Applications can override the reg properties of either
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* sram_data or sram_code nodes to change the balance of SRAM access partitioning.
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*/
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sram_data: memory@40000 {
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compatible = "mmio-sram";
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reg = <0x40000 DT_SIZE_K(960)>;
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};
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sram_code: memory@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(256)>;
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};
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};
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&smu1 {
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#address-cells = <1>;
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#size-cells = <1>;
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smu1_data: memory@0 {
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compatible = "zephyr,memory-region","mmio-sram";
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reg = <0x0 DT_SIZE_K(510)>;
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zephyr,memory-region = "SMU1";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
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};
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};
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&smu2 {
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#address-cells = <1>;
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#size-cells = <1>;
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smu2_data: memory@0 {
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compatible = "zephyr,memory-region","mmio-sram";
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reg = <0x0 DT_SIZE_K(140)>;
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zephyr,memory-region = "SMU2";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
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};
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};
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&peripheral {
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#address-cells = <1>;
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#size-cells = <1>;
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flexspi: spi@134000 {
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reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
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};
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clkctl0: clkctl@1000 {
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/* FIXME This chip does NOT have a syscon */
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compatible = "nxp,lpc-syscon";
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reg = <0x1000 0x1000>;
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#clock-cells = <1>;
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};
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pinctrl: mci_iomux@4000 {
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compatible = "nxp,mci-io-mux";
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reg = <0x4000 0x1000>;
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status = "okay";
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};
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clkctl1: clkctl@21000 {
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/* FIXME This chip does NOT have a syscon */
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compatible = "nxp,lpc-syscon";
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reg = <0x21000 0x1000>;
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#clock-cells = <1>;
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};
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rstctl0: reset@0 {
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compatible = "nxp,rstctl";
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reg = <0x0 0x80>;
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#reset-cells = <1>;
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};
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rstctl1: reset@20000 {
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compatible = "nxp,rstctl";
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reg = <0x20000 0x80>;
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#reset-cells = <1>;
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};
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pmu: pmu@31000 {
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reg = <0x31000 0x130>;
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compatible = "nxp,rw-pmu";
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pin0: pin0 {
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compatible = "nxp,aon-wakeup-pin";
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interrupts = <100 0>;
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status = "disabled";
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};
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pin1: pin1 {
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compatible = "nxp,aon-wakeup-pin";
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interrupts = <101 0>;
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status = "disabled";
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};
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};
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trng: random@14000 {
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compatible = "nxp,kinetis-trng";
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reg = <0x14000 0x1000>;
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status = "okay";
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interrupts = <123 0>;
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};
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wwdt: watchdog@e000 {
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compatible = "nxp,lpc-wwdt";
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reg = <0xe000 0x1000>;
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interrupts = <0 0>;
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status = "disabled";
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clk-divider = <1>;
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};
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hsgpio: hsgpio@100000 {
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compatible = "nxp,lpc-gpio";
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reg = <0x100000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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hsgpio0: gpio@0 {
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compatible = "nxp,lpc-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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int-source = "pint";
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};
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hsgpio1: gpio@1 {
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compatible = "nxp,lpc-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <1>;
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int-source = "pint";
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};
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};
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usb_otg: usbotg@145000 {
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compatible = "nxp,ehci";
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reg = <0x145000 0x200>;
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interrupts = <50 1>;
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interrupt-names = "usb_otg";
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num-bidir-endpoints = <8>;
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status = "disabled";
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};
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flexcomm0: flexcomm@106000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x106000 0x1000>;
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interrupts = <14 0>;
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clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
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resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
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dmas = <&dma0 0>, <&dma0 1>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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flexcomm1: flexcomm@107000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x107000 0x1000>;
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interrupts = <15 0>;
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clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
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resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
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dmas = <&dma0 2>, <&dma0 3>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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flexcomm2: flexcomm@108000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x108000 0x1000>;
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interrupts = <16 0>;
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clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
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resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
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dmas = <&dma0 4>, <&dma0 5>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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flexcomm3: flexcomm@109000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x109000 0x1000>;
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interrupts = <17 0>;
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clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
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resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
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dmas = <&dma0 6>, <&dma0 7>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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flexcomm14: flexcom@126000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x126000 0x2000>;
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interrupts = <20 0>;
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clocks = <&clkctl1 MCUX_FLEXCOMM14_CLK>;
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resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
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dmas = <&dma0 26>, <&dma0 27>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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aon_soc_ctrl: aon_soc_ctrl@5000800 {
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compatible = "nxp,rw-soc-ctrl";
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reg = <0x5000800 0x1000>;
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status = "okay";
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};
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soc_ctrl: soc_ctrl@5001000 {
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compatible = "nxp,rw-soc-ctrl";
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reg = <0x5001000 0x1000>;
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status = "okay";
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};
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pint: pint@25000 {
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compatible = "nxp,pint";
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reg = <0x25000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
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<35 2>, <36 2>, <37 2>, <38 2>;
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num-lines = <8>;
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num-inputs = <64>;
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};
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imu: nxp_wifi {
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compatible = "nxp,wifi";
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/* first index is the imu interrupt, the second is the wakeup done interrupt */
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interrupts = <72 2>, <64 2>;
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};
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dma0: dma-controller@104000 {
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compatible = "nxp,lpc-dma";
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reg = <0x104000 0x1000>;
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interrupts = <1 0>;
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status = "disabled";
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#dma-cells = <1>;
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dma-channels = <33>;
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};
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lcdic: lcdic@128000 {
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compatible = "nxp,lcdic";
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reg = <0x128000 0x52>;
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interrupts = <61 0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkctl1 MCUX_LCDIC_CLK>;
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dmas = <&dma0 0>;
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};
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ctimer0: ctimer@28000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x28000 0x1000>;
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interrupts = <10 0>;
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status = "disabled";
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clk-source = <1>;
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clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer1: ctimer@29000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x29000 0x1000>;
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interrupts = <11 0>;
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status = "disabled";
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clk-source = <1>;
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clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer2: ctimer@2a000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x2a000 0x1000>;
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interrupts = <39 0>;
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status = "disabled";
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clk-source = <1>;
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clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer3: ctimer@2b000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x2b000 0x1000>;
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interrupts = <13 0>;
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status = "disabled";
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clk-source = <1>;
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clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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sctimer: pwm@146000 {
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compatible = "nxp,sctimer-pwm";
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reg = <0x146000 0x1000>;
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interrupts = <12 0>;
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clocks = <&clkctl1 MCUX_SCTIMER_CLK>;
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status = "disabled";
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prescaler = <8>;
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#pwm-cells = <3>;
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};
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mrt0: mrt@2d000 {
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compatible = "nxp,mrt";
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reg = <0x2d000 0x100>;
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interrupts = <9 0>;
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num-channels = <4>;
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num-bits = <24>;
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clocks = <&clkctl1 MCUX_MRT_CLK>;
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resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>;
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#address-cells = <1>;
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#size-cells = <0>;
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mrt0_channel0: mrt0_channel@0 {
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compatible = "nxp,mrt-channel";
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reg = <0>;
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status = "disabled";
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};
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mrt0_channel1: mrt0_channel@1 {
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compatible = "nxp,mrt-channel";
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reg = <1>;
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status = "disabled";
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};
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mrt0_channel2: mrt0_channel@2 {
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compatible = "nxp,mrt-channel";
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reg = <2>;
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status = "disabled";
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};
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mrt0_channel3: mrt0_channel@3 {
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compatible = "nxp,mrt-channel";
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reg = <3>;
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status = "disabled";
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};
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};
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mrt1: mrt@3f000 {
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compatible = "nxp,mrt";
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reg = <0x3f000 0x100>;
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interrupts = <23 0>;
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num-channels = <4>;
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num-bits = <24>;
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clocks = <&clkctl1 MCUX_FREEMRT_CLK>;
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resets = <&rstctl0 NXP_SYSCON_RESET(2, 26)>;
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#address-cells = <1>;
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#size-cells = <0>;
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mrt1_channel0: mrt1_channel@0 {
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compatible = "nxp,mrt-channel";
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reg = <0>;
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status = "disabled";
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};
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mrt1_channel1: mrt1_channel@1 {
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compatible = "nxp,mrt-channel";
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reg = <1>;
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status = "disabled";
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};
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mrt1_channel2: mrt1_channel@2 {
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compatible = "nxp,mrt-channel";
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reg = <2>;
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status = "disabled";
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};
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mrt1_channel3: mrt1_channel@3 {
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compatible = "nxp,mrt-channel";
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reg = <3>;
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status = "disabled";
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};
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};
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dmic0: dmic@121000 {
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#address-cells=<1>;
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#size-cells=<0>;
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compatible = "nxp,dmic";
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reg = <0x121000 0x1000>;
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interrupts = <25 0>;
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status = "disabled";
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clocks = <&clkctl1 MCUX_DMIC_CLK>;
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pdmc0: dmic-channel@0 {
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reg = <0>;
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dmas = <&dma0 16>;
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status = "disabled";
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};
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pdmc1: dmic-channel@1 {
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reg = <1>;
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dmas = <&dma0 17>;
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status = "disabled";
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};
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pdmc2: dmic-channel@2 {
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reg = <2>;
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dmas = <&dma0 18>;
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status = "disabled";
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};
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pdmc3: dmic-channel@3 {
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reg = <3>;
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dmas = <&dma0 19>;
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status = "disabled";
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};
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};
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gau {
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ranges = <>;
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#address-cells = <1>;
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#size-cells = <1>;
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adc0: gau_adc0@38000 {
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compatible = "nxp,gau-adc";
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reg = <0x38000 0x100>;
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interrupts = <112 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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adc1: gau_adc1@38100 {
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compatible = "nxp,gau-adc";
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reg = <0x38100 0x100>;
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interrupts = <111 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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dac0: dac@38200 {
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compatible = "nxp,gau-dac";
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reg = <0x38200 0x30>;
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interrupts = <108 0>;
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status = "disabled";
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#io-channel-cells = <0>;
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};
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};
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os_timer: timers@13b000 {
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compatible = "nxp,os-timer";
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reg = <0x13b000 0x1000>;
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interrupts = <41 0>;
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status = "disabled";
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};
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nbu: nbu {
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compatible = "nxp,nbu";
|
|
interrupts = <90 2>, <82 2>;
|
|
interrupt-names = "nbu_rx_int", "wakeup_int";
|
|
};
|
|
|
|
hci: hci_ble {
|
|
compatible = "nxp,hci-ble";
|
|
};
|
|
|
|
hdlc_rcp_if: hdlc_rcp_if {
|
|
compatible = "nxp,hdlc-rcp-if";
|
|
interrupts = <90 2>, <82 2>;
|
|
interrupt-names = "hdlc_rcp_if_int", "wakeup_int";
|
|
};
|
|
|
|
enet: enet@138000 {
|
|
compatible = "nxp,enet";
|
|
reg = <0x138000 0x700>;
|
|
clocks = <&clkctl1 MCUX_ENET_CLK>;
|
|
enet_mac: ethernet {
|
|
compatible = "nxp,enet-mac";
|
|
interrupts = <115 0>;
|
|
interrupt-names = "COMMON";
|
|
nxp,mdio = <&enet_mdio>;
|
|
nxp,ptp-clock = <&enet_ptp_clock>;
|
|
status = "disabled";
|
|
};
|
|
enet_mdio: mdio {
|
|
compatible = "nxp,enet-mdio";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
enet_ptp_clock: ptp-clock {
|
|
compatible = "nxp,enet-ptp-clock";
|
|
interrupts = <116 0>;
|
|
status = "disabled";
|
|
clocks = <&clkctl1 MCUX_ENET_PLL>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&flexspi {
|
|
compatible = "nxp,imx-flexspi";
|
|
status = "disabled";
|
|
interrupts = <42 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clkctl1 MCUX_FLEXSPI_CLK>;
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <3>;
|
|
};
|