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e6dd68ec89
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be enabled, instead of relying of dependencies. To do that, introduce a new `CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected by SoC when it implemented global pointer (GP) initialization for relative addressing in its linker. `CONFIG_RISCV_GP` will be the default choice when `CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y` Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
38 lines
963 B
Plaintext
38 lines
963 B
Plaintext
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_NEORV32
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select RISCV
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_PRIVILEGED
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select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
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imply XIP
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if SOC_NEORV32
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config SOC_NEORV32_V1_8_6
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bool "v1.8.6"
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# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
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select ATOMIC_OPERATIONS_C
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config SOC_NEORV32_VERSION
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hex
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default 0x01080600 if SOC_NEORV32_V1_8_6
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help
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The targeted NEORV32 version as BCD-coded number. The format is
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identical to that of the NEORV32 Machine implementation ID (mimpid)
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register.
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config SOC_NEORV32_ISA_C
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bool "RISC-V ISA Extension \"C\""
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select RISCV_ISA_EXT_C
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help
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Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
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"C" extension (Compressed Instructions).
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endif # SOC_NEORV32
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