mirror of
https://github.com/zephyrproject-rtos/zephyr
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6e89842d3d
The base_address in the device configuration is used as a handle
to access an entity in memory. In C, we call that a 'pointer'.
Also in C, (versus, say, PL/M) we name these pointer things after
what they point not ('regs') not what they are ('base address').
Thus, we change the member to a pointer type and change its name.
This makes it compile cleanly regardless of machine pointer size,
while also cutting down on a bunch of casting noise.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
86 lines
2.4 KiB
C
86 lines
2.4 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* This file is a template for cmake and is not meant to be used directly!
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*/
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static void i2c_config_@NUM@(struct device *port);
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static const struct i2c_dw_rom_config i2c_config_dw_@NUM@ = {
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.config_func = i2c_config_@NUM@,
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.bitrate = DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_CLOCK_FREQUENCY,
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#if DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_PCIE
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.pcie = true,
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.pcie_bdf = DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS,
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.pcie_id = DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_SIZE,
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#endif
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};
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static struct i2c_dw_dev_config i2c_@NUM@_runtime = {
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.regs = (struct i2c_dw_registers *)
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DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS
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};
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DEVICE_AND_API_INIT(i2c_@NUM@, DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_LABEL,
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&i2c_dw_initialize,
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&i2c_@NUM@_runtime, &i2c_config_dw_@NUM@,
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POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
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&funcs);
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#ifndef DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE
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#define DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE 0
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#endif
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static void i2c_config_@NUM@(struct device *port)
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{
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ARG_UNUSED(port);
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#if DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_PCIE
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#if DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0 == PCIE_IRQ_DETECT
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/* PCI(e) with auto IRQ detection */
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BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS),
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"DW I2C PCI auto-IRQ needs CONFIG_DYNAMIC_INTERRUPTS");
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unsigned int irq;
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irq = pcie_wired_irq(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS);
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if (irq == PCIE_CONF_INTR_IRQ_NONE) {
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return;
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}
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irq_connect_dynamic(irq,
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DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_PRIORITY,
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i2c_dw_isr, DEVICE_GET(i2c_@NUM@),
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DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE);
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pcie_irq_enable(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS, irq);
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#else
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/* PCI(e) with fixed or MSI IRQ */
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IRQ_CONNECT(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0,
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DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_PRIORITY,
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i2c_dw_isr, DEVICE_GET(i2c_@NUM@),
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DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE);
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pcie_irq_enable(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS,
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DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0);
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#endif
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#else
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/* not PCI(e) */
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IRQ_CONNECT(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0,
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DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_PRIORITY,
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i2c_dw_isr, DEVICE_GET(i2c_@NUM@),
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DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE);
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irq_enable(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0);
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#endif
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}
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